Summary: after trying some time to differentiate our design with IFDEFs and Generates, we realized that it is not practical.
Now we maintain two source codes in parallel - one for each platform.
Use IFDEFs in top modules to remove/switch between modules and remove unnecessary ports and parameters.
Use Generates when you want to use the same modules in slightly different parametrization. Do not use these constructs to apply major changes to your design.
http://stackoverflow.com/questions/16642375/systemverilog-when-to-use-define-macro-vs-generate