JTAG Level Translation

http://www.freelabs.com/~whitis/electronics/jtag/

One of the big issues in making a JTAG pod is level translation. The state of level translation ICs leaves a LOT to be desired. You would think that there would be a lot of chips that you could apply 1.2-5V power and logic on port A and 1.2-5V (or 0V) power and logic on port B. Well, that isn't the case. Many level translators assume that one power bus will always be higher than the other. You also need to deal with hot plugging where signal lines might get connected before Vref. And you can have any combination of the POD and the target being powered up or down. TI has a voltage translator selection application note that is informative; it would be more useful if there were actually good parts to choose from. Pullup resistors should not be used to pull the output of a driver higher than its supply voltage. Also, many level translators don't work at 5V. Many level translators have output enable or direction signals but don't be surprised if the input is connected to the wrong supply voltage. Many 5V devices have TTL not CMOS levels, which must be taken into account when doing voltage translation. Very few translators go from 1.2 to 5V on either port, let alone both ports with either VCC higher. And good luck finding a suitable part that also has a second source.

Maxim has a level translation tips though not adequate for a serious pod.

A typical JTAG pod might have 3.3V logic and need to interface to 1.2 to 5V logic. This means the other side of the translator could have higher or lower supply voltage. If the POD uses 5V logic, conversion may be simpler.

The state of single directional voltage translation leaves enough to be desired; when dealing with bidirectional signals it gets worse. Bit programmable bidirectional signals, such as would be found on a GPIO port or on a JTAG pod that allows flexible pin assignments, are particularly problematic for level translation. It is one thing to translate a bidirectional signal when you have a direction signal to work with and another when the translator has to guess. Suppose you have a high level on a port A input. Is it high because the micro drove it high or is it high because the translator is driving it high because it thinks port B is being driven high. Voltage clamps with passive pullups don't have this problem but they have the usual issues with pullups.

74LVC1G125 - single gate tristate driver, in 5 pin packages. About $0.29 qty 1 at digikey. Input is either 3.3V or 5V, supply voltage 1.65 to 5.5V. Problem is, you need to stuff a lot of parts. When having a board assembled, you pay for each part placed plus setup charges for each unique part.
74LVC125 - you might expect it to act like a quadd 74LVC1G125 except supply voltage is limited to 3.6V and some are limited on the low end as well.
TI 1G99 is a single gate 8 pin device with 60 functions intended to reduce inventory. 1G97 and 1G98 have 9 functions and 6 pins. Not a programable device, it is a 4 input device with a fixed transfer function and you select the logic function based on how you tie the inputs. The LVC version works from 1.65 to 5V and has 5V tolerant inputs. Good for high to low translation, not so good for low to high though it may do 3.3V to 5V. There are however versions with voltage suffixes that might have fixed thresholds. 1T97 and 1T98 translator versions availible (3.6V max).
74LVC2T45, 74LCV2T45-1.8V, 74LVC2T45-2.5V, 74LVC2T46-3.3V, 74LVC2T45-5V. Dual gate (1T versions also available) dual supply translators. Samples only as of this writing except for the one with no suffix. "Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range". Dual bidirectional bus transceiver with common DIR signal. 74Mbps tranlating to 1.8V, faster for higher voltages. Goes into isolation mode when either power supply is lost.
FET clamp bus switches and Translation Voltage Clamps(TI). These are an array of symetrical fets with the gates all tied together and matched gate threshold voltages. The two busses are connected to source and drain. Voltage in either direction is clamped to the gate voltage minus the gate threshold. Either a simple external analog circuit (resistors) or an internal circuit is used to set the gate voltage. One FET is used as a reference. Internal circuits usually require one supply voltage to be less than the other. SN74TVC3010 (10 fets) and SN74TVC16222A are examples of the external bias type. One or two fewer signals than fets. These types of devices can also be used to isolate buses from each other. These are fast (Tpd 4ns) and bidirectional but when translating low to high need pullups and are only driven part of the way up before the pullup has to take over. To pass 5V through with no clamping requires an elevated supply. Versions are availible that can be connected in ways not shown on the datasheet to support any combination between 0v - 5V on either port; hint: use built in FETs for the reference circuit instead of one. If you also use a serial resistor (or the target board has one for protection), the series resistor and the pullup form a voltage divider that can give you less than ideal logic low levels. If you are receiving a signal from a driver with an active pullup but a passive pull down, it isn't going to interact well with your pullups. In any case, pullup resistors lower your input impedence. These parts can be useful for translation on a GPIO port where you have no direction signal availible. Maxim also has a variation on this. called a signal protector, with three fets in series that will protect signals to+/-40? volts; about 100 ohm series resistance and requres extra supply voltages such as +7.5V and -2.5V to bias the fets. The NXP GTL2000 looks like a pin compatible replacement for the SN74TVC16222A and the GTL2010 looks to be a pin compatible replacement for the SN74TVC16222A.
FET clamps with boosters. boosters can get confused about who is asserting what signal and friends have had bad things to say about such devices. ST2378E is one example, but it suffers from the requrement that VCCA > VCCB. Only 13Mhz.
bus hold type design made bidirectional, with boosters. Suppose you want to keep a bus from floating when tristated. You connect the bus to the inputs of a buffer and you connect the output of the buffer through a resistor back to the bus. Thus, the bus will be driven at whatever level it was last at until forced to another state. Put two suitable buffers with resisotrs back to back and you have a slow bidirectional voltage translator. To get around the speed, you add booster circuits (one shots with stronger drive). ADG3308 is an example. The MAX3000/3001/3002/3003 are this type, also availible in unidirectional (fixed number in each direction), but output drive is very weak (6k ohm) except when a transition occurs; 1.2 to 5.5V, some parts up to 20Mbps.
Open drain drivers with higher voltage tolerance on outputs. Unidirectional, requires pullups.
Analog switches. The TI LVC1G66 is a single analog switch that runs on 1.65 to 5.5V, 2ns propagation delay and 5.5 ohm on resistance. TI SN74LVC1G3157 is a SPDT analog switch, 1.65V to 5.5V, input up to 5.5V regardless of VCC (5V tolerant), Vih is 70% of VCC.
ATE pin drivers. Fairly expensive.
Overvoltage tolerant inputs with a suitable threshold. I have also used a logic level fet as an input translator but it does invert the signal. Getting a threshold that matches a range of logic levels can be tricky.
Some CPLDs can work fairly well for level translation applications and provide additional functionality as well. However, they are typically limited to translating up or down one knotch. I.E. a 3.3V device such as an XC9500XL family device may work with 5V, 3.3V, and 2.5V but not 1.2V and a 2.5V device may work with 1.2V, 2.5V, and 3.3V but not 5V. Some CPLDs have separate supply voltages for different I/O ports and some are simply tolerant of higher and lower levels. XAPP785 describes level translation using the coolrunner family (3.3V max).
Series resistors. Slow or low impedence issues. When using series resistors to down convert, make sure the device being driven has clamping diodes and that there is actually enough load on Vcc that the diodes can safely dump the current (the load on VCC may be negligable except when switching).
Comparators, Op amps, and differential receivers. Microchip TB013 has an example of using opamps and transistors to drive a signal.
Application specific translators such as SIM/smart card shifters. The MAX1840/MAX1841 are unusual in that they do not require that one VCC be always less than the other. Not enough I/Os, though. They have two drivers and one fet clamped bidirectional line.

Also consider whether you should have opto-isolators