Frm:IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language
Bit-selects extract a particular bit from a vector net, vector reg, integer variable, or time variable. The bit can be addressed using an expression. If the bit-select is out of the address bounds or the bit-select is x or z, then the value returned by the reference shall be x. The bit-select or part-select of a variable declared as real or realtime shall be considered illegal.
Several contiguous bits in a vector net, vector reg, integer variable, or time variable can be addressed and are known as part-selects. There are two types of part-selects, a constant part-select and an indexed part-select.
A constant part-select of a vector reg or net is given with the following syntax:
vect[msb_expr:lsb_expr]
Both expressions shall be constant expressions. The first expression has to address a more significant bit than the second expression. If the part-select is out of the address bounds or the part-select is x or z, then the value returned by the reference shall be x.
An indexed part select of a vector net, vector reg, integer variable, or time variable is given with the following syntax:
reg [15:0] big_vect; reg [0:15] little_vect; big_vect[lsb_base_expr +: width_expr] little_vect[msb_base_expr +: width_expr] big_vect[msb_base_expr -: width_expr] little_vect[lsb_base_expr -: width_expr]
The width_expr shall be a constant expression. It also shall not be affected by run-time parameter assignments. The lsb_base_expr and msb_base_expr can vary at run-time. The first two examples select bits starting at the base and ascending the bit range. The number of bits selected is equal to the width expression. The second two examples select bits starting at the base and descending the bit range. Part-selects that address a range of bits that are completely out of the address bounds of the net, reg, integer, or time, or when the part-select is x or z, shall yield the value x when read, and shall have no effect on the data stored when written.
Part-selects that are partially out of range shall when read return x for the bits that are out of range, and when written shall only affect the bits that are in range.
Examples:
module top; `timescale 10ns/1ns reg [31:0] big_vect = 'h12345678; reg [0:31] little_vect = 'h87654321; reg [63:0] dword; integer sel; initial begin #100 $display("1. big_vect = 0x%h, big_vect[0 +:8] is %h, and big_vect[7 -:8] is %h ", big_vect, big_vect[0 +:8], big_vect[7 -:8] ); if ( big_vect[0 +:8] == big_vect[7 : 0])begin $display(" big_vect[0 +:8] == big_vect[7 : 0]"); end if (little_vect[0 +:8] == little_vect[0 : 7])begin $display("little_vect[0 +:8] == little_vect[0 : 7]"); end if ( big_vect[15 -:8] == big_vect[15 : 8])begin $display(" big_vect[15 -:8] == big_vect[15 : 8]"); end if (little_vect[15 -:8] == little_vect[8 :15])begin $display("little_vect[15 -:8] == little_vect[8 :15]"); end if (sel >0 && sel < 8) dword[8*sel +:8] = big_vect[7:0]; // Replace the byte selected. // 注意： big_vect[0:7] 引用错误，同理little_vect[15:8] 也是引用错误。 // if ( big_vect[0 +:8] == big_vect[0 : 7])begin end end endmodule
output：
# 1. big_vect = 0x12345678, big_vect[0 +:8] is 78, and big_vect[7 -:8] is 78 # big_vect[0 +:8] == big_vect[7 : 0] # little_vect[0 +:8] == little_vect[0 : 7] # big_vect[15 -:8] == big_vect[15 : 8] # little_vect[15 -:8] == little_vect[8 :15]