定位到s3c-u-boot-1.1.6cpus3c64xxstart.s，打开该文件
1 /* 2 * armboot - Startup Code for S3C6400/ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 * 25 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 26 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by jsgood (jsgood.yang@samsung.com) 27 * Base codes by scsuh (sc.suh) 28 */ 29 30 #include <config.h> 31 #include <version.h> 32 #ifdef CONFIG_ENABLE_MMU 33 #include <asm/proc/domain.h> 34 #endif 35 #include <regs.h> 36 37 #ifndef CONFIG_ENABLE_MMU 38 #ifndef CFG_PHY_UBOOT_BASE 39 #define CFG_PHY_UBOOT_BASE CFG_UBOOT_BASE 40 #endif 41 #endif 42 以上代码主要检查CONFIG_ENABLE_MMU，已在/include/configs/smdk6410.h中定义 43 /* 44 ************************************************************************* 45 * 46 * Jump vector table as in table 3.1 in [1] 47 * 48 ************************************************************************* 49 */ 50 51 .globl _start 52 _start: b reset 53 ldr pc, _undefined_instruction 54 ldr pc, _software_interrupt 55 ldr pc, _prefetch_abort 56 ldr pc, _data_abort 57 ldr pc, _not_used 58 ldr pc, _irq 59 ldr pc, _fiq 60 //以上代码中的.globl相当于c语言中的extenal，而_start相对于C语言中使用goto语句时的调转标签，b是arm汇编中的不带返回的调转指令。最后的ldr命令，是Load Register的缩写，主要用于从存储器将一个32位的字数据送到目的寄存器中，最常用的用法是：
ldr pc,标号1
...
标号1：
.word 标号2
...
标号2：
... (具体执行的代码）
即，将地址为标号1的内容放入到pc，而地址为标号1中的内容正好又是标号2，所以去执行标号后的代码。
61 _undefined_instruction: 62 .word undefined_instruction 63 _software_interrupt: 64 .word software_interrupt 65 _prefetch_abort: 66 .word prefetch_abort 67 _data_abort: 68 .word data_abort 69 _not_used: 70 .word not_used 71 _irq: 72 .word irq 73 _fiq: 74 .word fiq 75 _pad: 76 .word 0x12345678 /* now 16*4=64 */ 77 .global _end_vect 78 _end_vect: 79 80 .balignl 16,0xdeadbeef
以上代码是接上面的代码，其中.word代码为其分别一个word=32bit=4Byte的地址空间；balignl表示字节对齐，即在此表示，接下来的代码，都要16字节对齐，不足之处，用0xdeadbeef填充。 81 /* 82 ************************************************************************* 83 * 84 * Startup Code (reset vector) 85 * 86 * do important init only if we don't start from memory! 87 * setup Memory and board specific bits prior to relocation. 88 * relocate armboot to ram 89 * setup stack 90 * 91 ************************************************************************* 92 */ 93 94 _TEXT_BASE: 95 .word TEXT_BASE 96 该值的具体地址在s3c-u-boot-1.1.6/board/samsung/smdk6410/config.mk中 97 /* 98 * Below variable is very important because we use MMU in U-Boot. 99 * Without it, we cannot run code correctly before MMU is ON. 100 * by scsuh. 101 */ 102 _TEXT_PHY_BASE: 103 .word CFG_PHY_UBOOT_BASE 104 105 .globl _armboot_start 106 _armboot_start: 107 .word _start 108 宏CFG_PHY_UBOOT_BASE定义内存地址
109 /* 110 * These are defined in the board-specific linker script. 111 */ 112 .globl _bss_start 113 _bss_start: 114 .word __bss_start 115 116 .globl _bss_end 117 _bss_end: 118 .word _end 119 如注释所示，该地址的值在s3c-u-boot/board/samsung/smdk6410/u-boot.lds中定义 120 #ifdef CONFIG_USE_IRQ 121 /* IRQ stack memory (calculated at run-time) */ 122 .globl IRQ_STACK_START 123 IRQ_STACK_START: 124 .word 0x0badc0de 125 126 /* IRQ stack memory (calculated at run-time) */ 127 .globl FIQ_STACK_START 128 FIQ_STACK_START: 129 .word 0x0badc0de 130 #endif 131 如注释所示，该地址的值中运行时计算得到 132 /* 133 * the actual reset code 134 */ 135 136 reset: 137 /* 138 * set the cpu to SVC32 mode 139 */ 140 mrs r0,cpsr 141 bic r0,r0,#0x1f 142 orr r0,r0,#0xd3 143 msr cpsr,r0 144 cpsr是Current Program Status Register的缩写，表示当前程序状态寄存器，与此对应的是SPSR.程序状态寄存器的格式为：
31 30 29 28 27-- 8 7 6 5 4 3 2 1 0
N Z C V Reserved I F T M4 M3 M2 M1 M0
其中：
mrs是Move From Status Register的缩写，用于将程序状态寄存器的内容传送到通用寄存器中；
bic是Bit Clear的缩写，用于清除操作数1的某些位，并把结果放置到目的寄存器中；
orr是Logical OR的缩写，用于将两个操作数进行逻辑与，并把结果放到目的寄存器中；
msr是Move To Status Register的缩写，将操作数的内容传送到程序状态寄存器中。
另外：
0x1f=00011111
0xdf=11011111 145 /* 146 ************************************************************************* 147 * 148 * CPU_init_critical registers 149 * 150 * setup important registers 151 * setup memory timing 152 * 153 ************************************************************************* 154 */ 155 /* 156 * we do sys-critical inits only at reboot, 157 * not when booting from ram! 158 */ 159 cpu_init_crit: 160 /* 161 * flush v4 I/D caches 162 */ 163 mov r0, #0 164 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 165 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 166 167 /* 168 * disable MMU stuff and caches 169 */ 170 mrc p15, 0, r0, c1, c0, 0 171 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 172 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 173 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 174 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 175 mcr p15, 0, r0, c1, c0, 0 176 177 /* Peri port setup */ 178 ldr r0, =0x70000000 179 orr r0, r0, #0x13 180 mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff) 181 以上代码，通过寄存器P15来设置，主要参考arm1176数据手册（它是6410）， 182 #ifdef CONFIG_BOOT_ONENAND 183 ldr r0, =0x70000000 @ onenand controller setup 184 orr r0, r0, #0x100000 185 ldr r1, =0x4000 186 orr r1, r1, #0xe0 187 str r1, [r0] 188 189 #if defined(CONFIG_S3C6410) || defined(CONFIG_S3C6430) 190 orr r0, r0, #300 @ disable watchdog 191 mov r1, #1 192 str r1, [r0] 193 194 mov r1, #0x23000000 @ start buffer register 195 orr r1, r1, #0x30000 196 orr r1, r1, #0xc800 197 #else 198 mov r1, =0x20000000 @ start buffer register 199 orr r1, r1, #0xc30000 200 orr r1, r1, #0xc800 201 #endif 202 203 sub r0, r1, #0x0400 @ start address1 register 204 205 ldr r2, [r1, #0x84] @ ecc bypass 206 orr r2, r2, #0x100 207 str r2, [r1, #0x84] 208 209 mov r3, #0x0 @ DFS, FBA 210 str r3, [r0, #0x00] 211 str r3, [r0, #0x04] @ select dataram for DDP as 0 212 213 mov r4, #0x104 @ interrupt register 214 mov r5, #0x0002 @ FPA, FSA 215 mov r6, #0x0800 @ BSA 216 217 onenand_bl1_load: 218 str r5, [r0, #0x1c] @ save FPA, FSA 219 orr r6, r6, #0x02 @ BSC 220 str r6, [r1, #0x00] @ save BSA, BSC 221 str r3, [r1, r4] @ clear interrupt 222 str r3, [r1, #0x80] @ write load command 223 224 mov r7, #0x100 @ need small delay 225 226 onenand_wait_loop1: 227 subs r7, r7, #0x1 228 bne onenand_wait_loop1 229 230 add r5, r5, #0x2 @ next FPA, FSA 231 sub r6, r6, #0x2 232 add r6, r6, #0x200 @ next BSA 233 cmp r5, #0x8 234 bne onenand_bl1_load 235 #endif 236 以上是通过onenand启动方式代码 237 /* 238 * Go setup Memory and board specific bits prior to relocation. 239 */ 240 bl lowlevel_init /* go setup pll,mux,memory */ 241 以上通过调用的函数，进行板纺初始化 242 /* when we already run in ram, we don't need to relocate U-Boot. 243 * and actually, memory controller must be configured before U-Boot 244 * is running in ram. 245 */ 246 ldr r0, =0xff000fff 247 bic r1, pc, r0 /* r0 <- current base addr of code */ 248 ldr r2, _TEXT_BASE /* r1 <- original base addr in ram */ 249 bic r2, r2, r0 /* r0 <- current base addr of code */ 250 cmp r1, r2 /* compare r0, r1 */ 251 beq after_copy /* r0 == r1 then skip flash copy */ 252 以上是 253 #ifdef CONFIG_BOOT_NOR /* relocate U-Boot to RAM */ 254 adr r0, _start /* r0 <- current position of code */ 255 ldr r1, _TEXT_PHY_BASE /* r1 <- destination */ 256 ldr r2, _armboot_start 257 ldr r3, _bss_start 258 sub r2, r3, r2 /* r2 <- size of armboot */ 259 add r2, r0, r2 /* r2 <- source end address */ 26 261 nor_copy_loop: 262 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 263 stmia r1!, {r3-r10} /* copy to target address [r1] */ 264 cmp r0, r2 /* until source end addreee [r2] */ 265 ble nor_copy_loop 266 b after_copy 267 #endif 268 以上是使用nor nand方式启动代码 269 #ifdef CONFIG_BOOT_NAND 270 mov r0, #0x1000 271 bl copy_from_nand 272 #endif 273 以上是通过调用，使用nand 方式启动代码 274 #ifdef CONFIG_BOOT_MOVINAND 275 ldr sp, _TEXT_PHY_BASE 276 bl movi_bl2_copy 277 b after_copy 278 #endif 279 以上是通过sd卡方式启动代码 280 #ifdef CONFIG_BOOT_ONENAND 281 ldr sp, =0x50000000 @ temporary stack 282 283 #ifdef CONFIG_S3C6400 284 mov r1, =0x20000000 @ start buffer register 285 orr r1, r1, #0xc30000 286 orr r1, r1, #0xc800 287 #else 288 mov r1, #0x23000000 @ start buffer register 289 orr r1, r1, #0x30000 290 orr r1, r1, #0xc800 291 #endif 292 293 ldr r2, [r1, #0x84] @ ecc bypass 294 orr r2, r2, #0x100 295 str r2, [r1, #0x84] 296 297 sub r0, r1, #0x0400 @ start address1 register 298 299 str r3, [r0, #0x00] 300 str r3, [r0, #0x04] @ select dataram for DDP as 0 301 302 mov r4, #0x104 @ interrupt register 303 304 mov r6, #0x0c00 @ fixed dataram1 sector number 305 str r6, [r1, #0x00] 306 307 mov r3, #0x0 @ DFS, FBA 308 mov r5, #0x0000 @ FPA, FSA 309 ldr r9, =CFG_PHY_UBOOT_BASE @ destination 310 311 onenand_bl2_load: 312 str r3, [r0, #0x00] @ save DFS, FBA 313 str r5, [r0, #0x1c] @ save FPA, FSA 314 315 mov r7, #0x0 @ clear interrupt 316 str r7, [r1, r4] 317 str r7, [r1, #0x80] @ write load command 318 319 mov r8, #0x1000 320 onenand_wait_loop2: 321 subs r8, r8, #0x1 322 bne onenand_wait_loop2 323 324 onenand_wait_int: @ wait INT and RI 325 ldr r7, [r1, r4] 326 mov r8, #0x8000 327 orr r8, r8, #0x80 328 tst r7, r8 329 beq onenand_wait_int 330 331 mov r7, #0x0 @ clear interrupt 332 str r7, [r1, r4] 333 334 mov r8, #0xc00 @ source address (dataram1) 335 mov r10, #0x40 @ copy loop count (64 = 2048 / 32) 336 337 stmia sp, {r0-r7} @ backup 338 339 onenand_copy_to_ram: 340 ldmia r8!, {r0-r7} 341 stmia r9!, {r0-r7} 342 subs r10, r10, #0x1 343 bne onenand_copy_to_ram 344 345 ldmia sp, {r0-r7} @ restore 346 347 add r5, r5, #0x4 @ next FPA 348 cmp r5, #0x100 @ last FPA? 349 bne onenand_bl2_load 350 351 /* next block */ 352 mov r5, #0x0 @ reset FPA 353 add r3, r3, #0x1 @ next FBA 354 cmp r3, #0x2 @ last FBA? 355 bne onenand_bl2_load 356 b after_copy 357 #endif 358 359 #ifdef CONFIG_BOOT_ONENAND_IROM 360 ldr sp, _TEXT_PHY_BASE 361 bl onenand_bl2_copy 362 b after_copy 363 #endif 364 以上是启动代码 365 after_copy: 366 #ifdef CONFIG_ENABLE_MMU 367 enable_mmu: 368 /* enable domain access */ 369 ldr r5, =0x0000ffff 370 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 371 372 /* Set the TTB register */ 373 ldr r0, _mmu_table_base 374 ldr r1, =CFG_PHY_UBOOT_BASE 375 ldr r2, =0xfff00000 376 bic r0, r0, r2 377 orr r1, r0, r1 378 mcr p15, 0, r1, c2, c0, 0 379 380 /* Enable the MMU */ 381 mmu_on: 382 mrc p15, 0, r0, c1, c0, 0 383 orr r0, r0, #1 /* Set CR_M to enable MMU */ 384 mcr p15, 0, r0, c1, c0, 0 385 nop 386 nop 387 nop 388 nop 389 #endif 390 391 skip_hw_init: 392 /* Set up the stack */ 393 stack_setup: 394 #ifdef CONFIG_MEMORY_UPPER_CODE 395 ldr sp, =(CFG_UBOOT_BASE + CFG_UBOOT_SIZE - 0xc) 396 #else 397 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ 398 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ 399 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ 400 #ifdef CONFIG_USE_IRQ 401 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) 402 #endif 403 sub sp, r0, #12 /* leave 3 words for abort-stack */ 404 405 #endif 406 407 clear_bss: 408 ldr r0, _bss_start /* find start of bss segment */ 409 ldr r1, _bss_end /* stop here */ 410 mov r2, #0x00000000 /* clear */ 411 412 clbss_l: 413 str r2, [r0] /* clear loop... */ 414 add r0, r0, #4 415 cmp r0, r1 416 ble clbss_l 417 418 ldr pc, _start_armboot 419 420 _start_armboot: 421 .word start_armboot 422 423 #ifdef CONFIG_ENABLE_MMU 424 _mmu_table_base: 425 .word mmu_table 426 #endif 427 428 /* 429 * copy U-Boot to SDRAM and jump to ram (from NAND or OneNAND) 430 * r0: size to be compared 431 * Load 1'st 2blocks to RAM because U-boot's size is larger than 1block(128k) size 432 */ 433 .globl copy_from_nand 434 copy_from_nand: 435 mov r10, lr /* save return address */ 436 437 mov r9, r0 438 /* get ready to call C functions */ 439 ldr sp, _TEXT_PHY_BASE /* setup temp stack pointer */ 440 sub sp, sp, #12 441 mov fp, #0 /* no previous frame, so fp=0 */ 442 mov r9, #0x1000 443 bl copy_uboot_to_ram 444 445 3: tst r0, #0x0 446 bne copy_failed 447 448 ldr r0, =0x0c000000 449 ldr r1, _TEXT_PHY_BASE 450 1: ldr r3, [r0], #4 451 ldr r4, [r1], #4 452 teq r3, r4 453 bne compare_failed /* not matched */ 454 subs r9, r9, #4 455 bne 1b 456 457 4: mov lr, r10 /* all is OK */ 458 mov pc, lr 459 460 copy_failed: 461 nop /* copy from nand failed */ 462 b copy_failed 463 464 compare_failed: 465 nop /* compare failed */ 466 b compare_failed 467 468 /* 469 * we assume that cache operation is done before. (eg. cleanup_before_linux()) 470 * actually, we don't need to do anything about cache if not use d-cache in U-Boot 471 * So, in this function we clean only MMU. by scsuh 472 * 473 * void theLastJump(void *kernel, int arch_num, uint boot_params); 474 */ 475 #ifdef CONFIG_ENABLE_MMU 476 .globl theLastJump 477 theLastJump: 478 mov r9, r0 479 ldr r3, =0xfff00000 480 ldr r4, _TEXT_PHY_BASE 481 adr r5, phy_last_jump 482 bic r5, r5, r3 483 orr r5, r5, r4 484 mov pc, r5 485 phy_last_jump: 486 /* 487 * disable MMU stuff 488 */ 489 mrc p15, 0, r0, c1, c0, 0 490 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 491 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 492 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 493 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 494 mcr p15, 0, r0, c1, c0, 0 495 496 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 497 498 mov r0, #0 499 mov pc, r9 500 #endif 501 /* 502 ************************************************************************* 503 * 504 * Interrupt handling 505 * 506 ************************************************************************* 507 */ 508 @ 509 @ IRQ stack frame. 510 @ 511 #define S_FRAME_SIZE 72 512 513 #define S_OLD_R0 68 514 #define S_PSR 64 515 #define S_PC 60 516 #define S_LR 56 517 #define S_SP 52 518 519 #define S_IP 48 520 #define S_FP 44 521 #define S_R10 40 522 #define S_R9 36 523 #define S_R8 32 524 #define S_R7 28 525 #define S_R6 24 526 #define S_R5 20 527 #define S_R4 16 528 #define S_R3 12 529 #define S_R2 8 530 #define S_R1 4 531 #define S_R0 0 532 533 #define MODE_SVC 0x13 534 #define I_BIT 0x80 535 536 /* 537 * use bad_save_user_regs for abort/prefetch/undef/swi ... 538 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 539 */ 540 541 .macro bad_save_user_regs 542 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 543 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 544 545 ldr r2, _armboot_start 546 sub r2, r2, #(CFG_MALLOC_LEN) 547 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack 548 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 549 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 550 551 add r5, sp, #S_SP 552 mov r1, lr 553 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 554 mov r0, sp @ save current stack into r0 (param register) 555 .endm 556 557 .macro irq_save_user_regs 558 sub sp, sp, #S_FRAME_SIZE 559 stmia sp, {r0 - r12} @ Calling r0-r12 560 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 561 stmdb r8, {sp, lr}^ @ Calling SP, LR 562 str lr, [r8, #0] @ Save calling PC 563 mrs r6, spsr 564 str r6, [r8, #4] @ Save CPSR 565 str r0, [r8, #8] @ Save OLD_R0 566 mov r0, sp 567 .endm 568 569 .macro irq_restore_user_regs 570 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 571 mov r0, r0 572 ldr lr, [sp, #S_PC] @ Get PC 573 add sp, sp, #S_FRAME_SIZE 574 subs pc, lr, #4 @ return & move spsr_svc into cpsr 575 .endm 576 577 .macro get_bad_stack 578 ldr r13, _armboot_start @ setup our mode stack (enter in banked mode) 579 sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool 580 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack 581 582 str lr, [r13] @ save caller lr in position 0 of saved stack 583 mrs lr, spsr @ get the spsr 584 str lr, [r13, #4] @ save spsr in position 1 of saved stack 585 586 mov r13, #MODE_SVC @ prepare SVC-Mode 587 @ msr spsr_c, r13 588 msr spsr, r13 @ switch modes, make sure moves will execute 589 mov lr, pc @ capture return pc 590 movs pc, lr @ jump to next instruction & switch modes. 591 .endm 592 593 .macro get_bad_stack_swi 594 sub r13, r13, #4 @ space on current stack for scratch reg. 595 str r0, [r13] @ save R0's value. 596 ldr r0, _armboot_start @ get data regions start 597 sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool 598 sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack 599 str lr, [r0] @ save caller lr in position 0 of saved stack 600 mrs r0, spsr @ get the spsr 601 str lr, [r0, #4] @ save spsr in position 1 of saved stack 602 ldr r0, [r13] @ restore r0 603 add r13, r13, #4 @ pop stack entry 604 .endm 605 606 .macro get_irq_stack @ setup IRQ stack 607 ldr sp, IRQ_STACK_START 608 .endm 609 610 .macro get_fiq_stack @ setup FIQ stack 611 ldr sp, FIQ_STACK_START 612 .endm 613 614 /* 615 * exception handlers 616 */ 617 .align 5 618 undefined_instruction: 619 get_bad_stack 620 bad_save_user_regs 621 bl do_undefined_instruction 622 623 .align 5 624 software_interrupt: 625 get_bad_stack_swi 626 bad_save_user_regs 627 bl do_software_interrupt 628 629 .align 5 630 prefetch_abort: 631 get_bad_stack 632 bad_save_user_regs 633 bl do_prefetch_abort 634 635 .align 5 636 data_abort: 637 get_bad_stack 638 bad_save_user_regs 639 bl do_data_abort 640 641 .align 5 642 not_used: 643 get_bad_stack 644 bad_save_user_regs 645 bl do_not_used 646 647 #ifdef CONFIG_USE_IRQ 648 649 .align 5 650 irq: 651 get_irq_stack 652 irq_save_user_regs 653 bl do_irq 654 irq_restore_user_regs 655 656 .align 5 657 fiq: 658 get_fiq_stack 659 /* someone ought to write a more effiction fiq_save_user_regs */ 660 irq_save_user_regs 661 bl do_fiq 662 irq_restore_user_regs 663 664 #else 665 666 .align 5 667 irq: 668 get_bad_stack 669 bad_save_user_regs 670 bl do_irq 671 672 .align 5 673 fiq: 674 get_bad_stack 675 bad_save_user_regs 676 bl do_fiq 677 678 #endif 679 .align 5 680 .global arm1136_cache_flush 681 arm1136_cache_flush: 682 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 683 mov pc, lr @ back to caller 684 685 #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) 686 /* Use the IntegratorCP function from board/integratorcp/platform.S */ 687 #elif defined(CONFIG_S3C64XX) 688 /* For future usage of S3C64XX*/ 689 #else 690 .align 5 691 .globl reset_cpu 692 reset_cpu: 693 ldr r1, rstctl /* get addr for global reset reg */ 694 mov r3, #0x2 /* full reset pll+mpu */ 695 str r3, [r1] /* force reset */ 696 mov r0, r0 697 _loop_forever: 698 b _loop_forever 699 rstctl: 700 .word PM_RSTCTRL_WKUP 701 702 #endif