网卡寄存器分类
1. 若是PHY芯片，只存在MII寄存器即可，可直接访问，如dm9161a。
The DM9161A management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) for registers 0 through 6 with vendor-specific registers 16,17, 18, 21, 22, 23 and 24.
2. 若是MAC+PHY芯片，则除了MII寄存器外，还存在芯片本身的控制状态寄存器，如dm9000cep。
The DM9000C implements several control and status registers, which can be accessed by the host. These CSRs are byte aligned. All CSRs are set to their default values by hardware or software reset unless they are specified
3. 有的网卡芯片（PHY）包含3类寄存器，如AR8033。
Three types of registers are present on AR8033:
>> IEEE defined 32 MII
registers, referred to as “registers” in this document
– MII registers are accessed directly through the management frame.
>> Atheros defined debug
registers, referred to as “debug registers” in this document
– Write debug offset address to 0x1D
– Read/write the data from/to 0x1E
>> IEEE defined MDIO Manageable
Device (MMD) register, referred to as “MMD registers” in this document
– MMD register access: refer to “MDIO Interface Register”.
Example: Writing 0x8000 to register 0 of MMD3.
1. Write 0x3 to register 0xD: 0xD = 0x0003; (function = address; set the device
address)
2. Write 0x0 to register 0xE: 0xE = 0x0; (set the register offset address)
3. Write 0x4003 to register 0xD:0xD=0x4003; (function = data; keep the device
address)
4. Read register 0xE:0xE == (data from register 0x0 of MMD3)
5. Write 0x8000 to register 0xE: 0xE = 0x8000 (write 0x8000 to register 0x0 of
MMD3)
NOTE: Read operation follows the
process 1 to 4.
MDIO interface registers are categorized to two groups:
>>MMD3 – MDIO Manageable Device Address 3 for PCS
>>MMD7 – MDIO Manageable Device Address 7 for Auto-Negotiation
寄存器访问
下面以ar8033为例说明寄存器访问情况。
ar8033的MII寄存器可以直接访问，debug寄存器和MDIO寄存器需要借助MII寄存器进行访问。
MDIO寄存器风味两组MMD3和MMD7，其访问需要借助MMD Access Control Register (0xD)和MMD Access Address Data Register (0xE)。
offset:0x0E, or 0d14
