摘自 特权同学的《深入浅出玩转FPGA》
module sys_ctrl( input clk, // System input clock, 10MHz input rst_n, // System input reset signal output wire sys_rst_n, // System Reset , active low output wire clk_25m, // PLL output clock output wire clk_100m // PLL output clock ); wire locked; // PLL lock wire pll_rst; // reset signal for PLL reg rst_r1, rst_r2; //异步复位，同步释放，防止亚稳态 always@(posedge clk or negedge rst_n) if (!rst_n) rst_r1 <= 1'b1; else rst_r1 <= 1'b0; always@(posedge clk or negedge rst_n) if (!rst_n) rst_r2 <= 1'b1; else rst_r2 <= rst_r1; assign pll_rst = rst_r2; wire sysrst_nr0; reg sysrst_nr1, sysrst_nr2; assign sysrst_nr0 = rst_n & locked; always@(posedge clk_100m or negedge sysrst_nr0) if (!sysrst_nr0) sysrst_nr1 <= 1'b0; else sysrst_nr1 <= 1'b1; always@(posedge clk_100m or negedge sysrst_nr0) if (!sysrst_nr0) sysrst_nr2 <= 1'b0; else sysrst_nr2 <= sysrst_nr1; assign sys_rst_n = sysrst_nr2; PLL_ctrl uut_PLL_ctrl( .areset(pll_rst), .inclk0(clk), .c0(clk_25m), .c1(clk_100m), .locked(locked) ); endmodule