Time
2020.11.1
Summary
Examines simultaneous multithreading
We present several models of simulatneous multithreading and compare them with alternative organizations:
a wide supersclar,a fine-grain multithreaded processor,single-chip,multiple-issue multiprocessing architectures
Our results show that both (single-threaded) superscalar and fine-grain multithreaded rchitectures are limited in their ability to utilize the resources of a wide-issue processor. Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multithreading
We evaluate several cache configurations made possible by this type of organization and evaluate tradeoffs between them.
Structure
1 Introduction
Figure 1:Empty issue slots can be defined as either vertical waste or horizontal waste.
2 Methodology
2.1 Simulation Environment
Table 1:Simulated instruction latencies（模拟指令延迟 ）
Table 2:Details of the cahce hierarchy
2.2 Workload
3 Superscalar Bottlenecks: Where Have All the Cycles Gone?
Figure 2:Sources of all unused issue cycles in an 8-issue superscalar processor.
Table 3:All possible causes of wasted issue slots,and Possible Latency-Hiding or Latency-Reducing Technique
4 Simultaneous Multithreading
4.1 The Machine Models
Table 4:A comparison of key hardware complexity features of the various models
4.2 The Performance of Simultaneous Multithreading
Figure 3:Instruction throughtput as a function of the number of threads（指令吞吐量与线程数的关系）
5 Cache Design for a Simultaneous Multithreaded Processor
Figure 4:Results for the simulated cache configurations,shown relative to the throughput(instructions per cycle) of the 64s.64p cache results
6 Simultaneous Multithreading versus Single-Chip Multiprocessing
Figure 5:Results for the various multiprocessor vs. simultaneous multithreding comparisons.
7 Related Work
8 Summary
Research Objective
simultaneous multithreading
what is simultaneous multithreading?
a techniquee permitting several independent threads to issue instruction to a superscalar's multiple functional units in a single cycle.
允许多个独立线程在单个tradeoffs周期内向超标量的多个功能单元发出指令的技术
Words
single-issue-pipeline microprocessor design
单发射微处理器设计
deeply pipelined wide-issue processors
深流水宽发射处理器