Verilog实现Matlab的fliplr函数

1 genvar i;
2 generate
3    for ( i=0; i<24; i=i+1)
4    begin: fliplr
5       assign reg_head_24bit[i] = reg_head_ckwn[23-i];
6    end
7 endgenerate

原文地址:https://www.cnblogs.com/achangchang/p/12809370.html