FPGA测试（验证）之——自动仿真

#quit and clear
quit   -sim
.main  clear
#Creat libraries folder path, example : vlib ./
vlib   work

#Map logic lib to folder path, example:
vmap   work   work

#---------------------------------------------Replaced with the filelist.f--------------------------------------------
#Compile verilog Code ,exmaple : vlog -work [logic library's name] [the will Compiled file's path and name ]
#IP core
vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/ip/pll_50m_73m/pll_50m_73m.v}
vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/ip/pll_50m_73m/pll_50m_73m/pll_50m_73m_0002.v}

vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/ip/pll_73m_92m/pll_73m_92m.v}
vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/ip/pll_73m_92m/pll_73m_92m/pll_73m_92m_0002.v}

vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/ip/cv_serdes_rx_0/cv_serdes_rx_0.v}

vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/ip/async_fifo_rx_0/async_fifo_rx_0.v}

#RTL
vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/rtl/async_fifo_rx.v}
vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/rtl/frame_align.v}

#TOP
#vlog -vlog01compat -work work {D:/intel_pro/pet_trig/rtl/top.v}

#TB
vlog -vlog01compat -work work {D:/intel_pro/anc_back_end/rtl/tb.v}

#vlog -vlog01compat -work work -f {./filelist.f} //后续通过自动化脚本，实现上述工程 .v文件 自动加载
#---------------------------------------------Replaced with the filelist.f--------------------------------------------

#Start-up simulation example :
#vsim -t 1ns -L [logic library1] -L [logic library2] ... -voptargs=+acc [logic library of the tb file].[tb's name]
vsim -t 1ps -novopt -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L work -voptargs="+acc" tb

#add  wave | divider | color | group
add  wave  -group  pll_50m_73m            tb/u_pll_50m_73m/*
add  wave  -group  pll_73m_92m            tb/u_pll_73m_92m/*
add  wave  -group  cv_serdes_rx           tb/u_cv_serdes_rx_0/*
add  wave  -group  async_fifo_rx          tb/u_async_fifo_rx/*
add  wave  -group  cv_fifo_ip             tb/u_async_fifo_rx/u_async_fifo_rx_0/*
add  wave  -group  frame_align            tb/u_frame_align/*

#run time
run  1000000ms

上述代码为 sim.do 文件

vsim -do sim.do

上述代码为 run.bat 文件