FPGA测试（验证）之——灌入激励与结果保存

`timescale 1ns/1ps

module tb_top ();

reg                                         clk                 ;   //10MHz
reg                                         i_adc_dout1         ;
reg                                         i_adc_dout2         ;
wire                                        o_cnvst_n           ;
wire                                        o_sclk              ;
wire                                        tx                  ;
    
reg                     [13:0]              adc_i [69605:0] ;
reg                     [13:0]              adc_q [69605:0] ;

reg                     [ 3:0]              byte_cnt  = 4'd13;   //0~13
reg                     [19:0]              point_cnt = 20'd0;   //0~69605

reg                     [19:0]              iir_cnt_i  = 20'd0;   //0~69605
reg                     [19:0]              iir_cnt_q  = 20'd0;   //0~69605
reg                     [19:0]              mf_cnt_i   = 20'd0;   //0~69605
reg                     [19:0]              mf_cnt_q   = 20'd0;   //0~69605

parameter                                   WR_CNT = 69605;

//--------------------------------------------------------------------------------//
//-----------------------------------main  code-----------------------------------//
//--------------------------------------------------------------------------------//
Radar u_Radar (
    .inclk_10MHz                        ( clk                       ),
    .i_adc_dout1                        ( i_adc_dout1               ),
    .i_adc_dout2                        ( i_adc_dout2               ),
    .o_cnvst_n                          ( o_cnvst_n                 ),
    .o_sclk                             ( o_sclk                    ),
    .tx                                 ( tx                        )
);

initial begin
    clk = 1'b0;
    forever begin 
        #50 clk = 1'b1;  //时钟周期为100ns
        #50 clk = 1'b0;
    end
end

//initial begin
//    rst_n = 1'b0;
//    #2000 rst_n = 1'b1;  //复位2us
//end

//-------------------------------------------------------
// 从txt读取ADC输出数据
//-------------------------------------------------------
always @( posedge o_sclk ) begin
    if (byte_cnt > 4'd0) begin
        byte_cnt <= byte_cnt - 4'd1;
    end
    else begin
        byte_cnt <= 4'd13;
    end
end

always @( posedge o_sclk ) begin
    if (point_cnt < 69605) begin
        if (byte_cnt == 4'd0) begin
            point_cnt <= point_cnt + 20'd1;
        end
        else;
    end
    else begin
        point_cnt <= 20'd0;
    end
end

initial begin
    $readmemh ("D:/test_data/in/dataset1_I_hex.txt", adc_i);
    $readmemh ("D:/test_data/in/dataset1_Q_hex.txt", adc_q);
end

//initial begin
//    $readmemh ("D:/test_data/in/dataset2_I_hex.txt", adc_i);
//    $readmemh ("D:/test_data/in/dataset2_Q_hex.txt", adc_q);
//end

//-------------------------------------------------------
// 按时序串行输出ADC数据
//-------------------------------------------------------
always @( posedge o_sclk ) begin
    i_adc_dout1 <= adc_i[point_cnt][byte_cnt];
    i_adc_dout2 <= adc_q[point_cnt][byte_cnt];
end

always @( negedge o_sclk ) begin
    $display("adc_i[%d]: %h; i_adc_dout1: %b", point_cnt, adc_i[point_cnt], i_adc_dout1, "
"); // i_adc_dout1
    $display("adc_q[%d]: %h; i_adc_dout2: %b", point_cnt, adc_q[point_cnt], i_adc_dout2, "
"); // i_adc_dout2
end

//-------------------------------------------------------
// IIR滤波器输出数据保存
//-------------------------------------------------------
//IIR滤波器I路数据保存
integer iir_out_I_1;
initial iir_out_I_1 = $fopen("D:/test_data/out/iir_out_I_1.txt", "w");

always @(negedge tb_top.u_Radar.u_iir_btwth_hpf_i.vld_out) begin
    if(iir_cnt_i==0) begin
        iir_cnt_i <= iir_cnt_i + 20'd1;
    end
    else if((iir_cnt_i>=1) && (iir_cnt_i <= WR_CNT)) begin
        $fwrite (iir_out_I_1, "%d
", $signed(tb_top.u_Radar.u_iir_btwth_hpf_i.dat_out));
        iir_cnt_i <= iir_cnt_i + 20'd1;
    end
    else begin
        $fclose(iir_out_I_1);
    end
end

//IIR滤波器Q路数据保存
integer iir_out_Q_1;
initial iir_out_Q_1 = $fopen("D:/test_data/out/iir_out_Q_1.txt", "w");

always @(negedge tb_top.u_Radar.u_iir_btwth_hpf_q.vld_out) begin
    if(iir_cnt_q==0) begin
        iir_cnt_q <= iir_cnt_q + 20'd1;
    end
    else if((iir_cnt_q>=1) && (iir_cnt_q <= WR_CNT)) begin
        $fwrite (iir_out_Q_1, "%d
", $signed(tb_top.u_Radar.u_iir_btwth_hpf_q.dat_out));
        iir_cnt_q <= iir_cnt_q + 20'd1;
    end
    else begin
        $fclose(iir_out_Q_1);
    end
end

//-------------------------------------------------------
// MF滤波器输出数据保存
//-------------------------------------------------------
//MF滤波器I路数据保存
integer mf_out_I_1;
initial mf_out_I_1 = $fopen("D:/test_data/out/mf_out_I_1.txt", "w");

always @(negedge tb_top.u_Radar.u_filter_mf_i.o_mf_valid) begin
    if(mf_cnt_i==0) begin
        mf_cnt_i <= mf_cnt_i + 20'd1;
    end
    else if((mf_cnt_i>=1) && (mf_cnt_i <= WR_CNT)) begin
        $fwrite (mf_out_I_1, "%d
", $signed(tb_top.u_Radar.u_filter_mf_i.o_mf_data));
        mf_cnt_i <= mf_cnt_i + 20'd1;
    end
    else begin
        $fclose(mf_out_I_1);
    end
end

//MF滤波器Q路数据保存
integer mf_out_Q_1;
initial mf_out_Q_1 = $fopen("D:/test_data/out/mf_out_Q_1.txt", "w");

always @(negedge tb_top.u_Radar.u_filter_mf_q.o_mf_valid) begin
    if(mf_cnt_q==0) begin
        mf_cnt_q <= mf_cnt_q + 20'd1;
    end
    else if((mf_cnt_q>=1) && (mf_cnt_q <= WR_CNT)) begin
        $fwrite (mf_out_Q_1, "%d
", $signed(tb_top.u_Radar.u_filter_mf_q.o_mf_data));
        mf_cnt_q <= mf_cnt_q + 20'd1;
    end
    else begin
        $fclose(mf_out_Q_1);
    end
end

endmodule