//P0.0
/* SW_6 is at P0.1 */
#define HAL_KEY_SW_6_PORT P0
#define HAL_KEY_SW_6_BIT BV(0)
#define HAL_KEY_SW_6_SEL P0SEL
#define HAL_KEY_SW_6_DIR P0DIR
/* edge interrupt */
#define HAL_KEY_SW_6_EDGEBIT BV(0)
#define HAL_KEY_SW_6_EDGE HAL_KEY_RISING_EDGE//HAL_KEY_FALLING_EDGE
/* SW_6 interrupts */
#define HAL_KEY_SW_6_IEN IEN1 /* CPU interrupt mask register */
#define HAL_KEY_SW_6_IENBIT BV(5) /* Mask bit for all of Port_0 */
#define HAL_KEY_SW_6_ICTL P0IEN /* Port Interrupt Control register */
#define HAL_KEY_SW_6_ICTLBIT BV(0) /* P0IEN - P0.1 enable/disable bit */
#define HAL_KEY_SW_6_PXIFG P0IFG /* Interrupt flag at source */
//P0.1
/* SW_6 is at P0.1 */
#define HAL_KEY_SW_6_PORT P0
#define HAL_KEY_SW_6_BIT BV(0)
#define HAL_KEY_SW_6_SEL P0SEL
#define HAL_KEY_SW_6_DIR P0DIR
/* edge interrupt */
#define HAL_KEY_SW_6_EDGEBIT BV(1)
#define HAL_KEY_SW_6_EDGE HAL_KEY_RISING_EDGE//HAL_KEY_FALLING_EDGE
/* SW_6 interrupts */
#define HAL_KEY_SW_6_IEN IEN1 /* CPU interrupt mask register */
#define HAL_KEY_SW_6_IENBIT BV(5) /* Mask bit for all of Port_0 */
#define HAL_KEY_SW_6_ICTL P0IEN /* Port Interrupt Control register */
#define HAL_KEY_SW_6_ICTLBIT BV(1) /* P0IEN - P0.1 enable/disable bit */
#define HAL_KEY_SW_6_PXIFG P0IFG /* Interrupt flag at source */