MIPS Examples of Instructions on DLX

MIPS64 Architecture for Programmers Vloume

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To understand these tables we need to introduce notations of the description language.

A subscript is appended to the symbol <- whenever the length of the datum being tranferred might not be clear. Thus, <- _n mean transfer an n -bit quantity.
A subscript is used to indicate selection of a bit from a field. Bits are labeled from the most-significant bit starting at 0. The subscript may be a single digit (e.g. Regs[R4] ₀ yields the sign bit of R4) or a subrange (e.g. Regs[R3] _24..31 yields the least-significant byte of R3).
The variable Mem, used as an array that stands for main memory, is indexed by a byte address and may transfer any number of bytes.
A superscript is used to replicate a fields (e.g. 0 ²⁴ yields a fiels of zeros of length 24 bits).
The symbol ## is used to concatenate two fields and may appear on either side of a data transfer.

Examples of arithmetic/logical instructions on DLX
Example instruction	Instruction name	Meaning
ADD R1, R2, R3	Add	Regs[R1] <- Regs[R2]+Regs[R3]
ADDI R1, R2, #3	Add immediate	Regs[R1] <- Regs[R2] + 3
LHI R1, #42	Load high immediate	Regs[R1] <- 42##0¹⁶
SLLI R1, R2, #5	Shift left logical immediate	Regs[R1] <- Regs[R2] << 5
SLT R1, R2, R3	Set less than	if (Regs[R2]<Regs[R3]) Regs[R1] <- 1 else Regs[R1] <- 0

The load and store instructions in DLX
Example instruction	Instruction name	Meaning
LW R1,30(R2)	Load word	Regs[R1] <-₃₂Mem[30+Regs[R2]]
LW R1,1000(R0)	Load word	Regs[R1] <-₃₂Mem[1000+0] ; Register R0 always contains 0
LB R1,40(R3)	Load byte	Regs[R1] <-₃₂(Mem[40+Regs[R3]]₀)²⁴##Mem[40+Regs[R3]]
LBU R1,40(R3)	Load byte unsigned	Regs[R1] <-₃₂0²⁴ ## Mem[40+Regs[R3]]
LH R1,40(R3)	Load half word	Regs[R1] <-₃₂(Mem[40+Regs[R3]]₀)¹⁶ ## Mem[40+Regs[R3]] ## Mem[41+Regs[R3]]
LF F0,50(R3)	Load float	Regs[F0] <-₃₂Mem[50+Regs[R3]]
LD FO,50(R2)	Load double	Regs[F0] ##Regs[F1]<-₆₄Mem[50+Regs[R2]]
SW 500(R4),R3	Store word	Mem[500+Regs[R4]] <-₃₂Regs[R3]
SF 40(R3),F0	Store float	Mem[40+Regs[R3]] <-₃₂Regs[F0]
SD 40(Re),F0	Store double	Mem[40+Regs[R3]] <-₃₂Regs[F0]; Mem[44+Regs[R3]] <-₃₂Regs[F1]
SH 502(R2),R3	Store half	Mem[502+Regs[R2]] <-₁₆Regs[R3]_16..31
SB 41(R3),R2	Store byte	Mem[41+Regs[R3]] <-₈Regs[R2]_24..31

Typical control-flow instructions in DLX
Example instruction	Instruction name	Meaning
J name	Jump	PC<-name; ((PC+4)-2²⁵) <= name< ((PC+4)+2²⁵)
JAL name	Jump and link	R31<-PC+4; PC<-name; ((PC+4)-2²⁵)<=name<((PC+4)+2²⁵)
JALR R2	Jump and link register	Regs[R31]<-PC+4; PC , Regs[R2]
JR R3	Jump register	PC <- Regs[R3]
BEQZ R4, name	Branch equal zero	if (Regs[R4]==0) PC<-name; ((PC+4)-2¹⁵)<=name<((PC+4)+2¹⁵)
BNEZ R4, name	Branch not equal zero	if (Regs[R4]!=0) PC<-name; ((PC+4)-2¹⁵)<=name<((PC+4)+2¹⁵)

ADD is the MIPS32 instruction, DADD is for MIPS64 where registers are 64-bits wide rather than 32.