常用函数
rtems_interrupt_catch
intrcatch.c cpukit temssrc 1468 2003/9/5 11
/* rtems_interrupt_catch * * This directive allows a thread to specify what action to take when * catching signals. * * Input parameters: * new_isr_handler - address of interrupt service routine (isr) * vector - interrupt vector number * old_isr_handler - address at which to store previous ISR address * * Output parameters: * RTEMS_SUCCESSFUL - always succeeds * *old_isr_handler - previous ISR address */ rtems_status_code rtems_interrupt_catch( rtems_isr_entry new_isr_handler, rtems_vector_number vector, rtems_isr_entry *old_isr_handler ) { if ( !_ISR_Is_vector_number_valid( vector ) ) return RTEMS_INVALID_NUMBER; if ( !_ISR_Is_valid_user_handler( (void *) new_isr_handler ) ) return RTEMS_INVALID_ADDRESS; if ( !_ISR_Is_valid_user_handler( (void *) old_isr_handler ) ) return RTEMS_INVALID_ADDRESS; _ISR_Install_vector( vector, (proc_ptr)new_isr_handler, (proc_ptr *)old_isr_handler ); return RTEMS_SUCCESSFUL; }
isr.h cpukitscoreinclude temsscore 6447 2003/9/5
/* * _ISR_Install_vector * * DESCRIPTION: * * This routine installs new_handler as the interrupt service routine * for the specified vector. The previous interrupt service routine is * returned as old_handler. */ #define _ISR_Install_vector( _vector, _new_handler, _old_handler ) _CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
cpu.c cpukitscorecpusparc 9248 2003/9/5 81
/*PAGE * * _CPU_ISR_install_vector * * This kernel routine installs the RTEMS handler for the * specified vector. * * Input parameters: * vector - interrupt vector number * new_handler - replacement ISR for this vector number * old_handler - pointer to former ISR for this vector number * * Output parameters: * *old_handler - former ISR for this vector number * */ void _CPU_ISR_install_vector( unsigned32 vector, proc_ptr new_handler, proc_ptr *old_handler ) { unsigned32 real_vector; proc_ptr ignored; /* * Get the "real" trap number for this vector ignoring the synchronous * versus asynchronous indicator included with our vector numbers. */ real_vector = SPARC_REAL_TRAP_NUMBER( vector ); /* * Return the previous ISR handler. */ *old_handler = _ISR_Vector_table[ real_vector ]; /* * Install the wrapper so this ISR can be invoked properly. */ _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); /* * We put the actual user ISR address in '_ISR_vector_table'. This will * be used by the _ISR_Handler so the user gets control. */ _ISR_Vector_table[ real_vector ] = new_handler; }
/* * The following declares the Vector Table. Application * interrupt service routines are vectored by the ISR Handler via this table. */ SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table;
cpu.c cpukitscorecpusparc 9248 2003/9/5 81
/*PAGE * * _CPU_ISR_install_raw_handler * * This routine installs the specified handler as a "raw" non-executive * supported trap handler (a.k.a. interrupt service routine). * * Input Parameters: * vector - trap table entry number plus synchronous * vs. asynchronous information * new_handler - address of the handler to be installed * old_handler - pointer to an address of the handler previously installed * * Output Parameters: NONE * *new_handler - address of the handler previously installed * * NOTE: * * On the SPARC, there are really only 256 vectors. However, the executive * has no easy, fast, reliable way to determine which traps are synchronous * and which are asynchronous. By default, synchronous traps return to the * instruction which caused the interrupt. So if you install a software * trap handler as an executive interrupt handler (which is desirable since * RTEMS takes care of window and register issues), then the executive needs * to know that the return address is to the trap rather than the instruction * following the trap. * * So vectors 0 through 255 are treated as regular asynchronous traps which * provide the "correct" return address. Vectors 256 through 512 are assumed * by the executive to be synchronous and to require that the return address * be fudged. * * If you use this mechanism to install a trap handler which must reexecute * the instruction which caused the trap, then it should be installed as * an asynchronous trap. This will avoid the executive changing the return * address. */ void _CPU_ISR_install_raw_handler( unsigned32 vector, proc_ptr new_handler, proc_ptr *old_handler ) { unsigned32 real_vector; CPU_Trap_table_entry *tbr; CPU_Trap_table_entry *slot; unsigned32 u32_tbr; unsigned32 u32_handler; /* * Get the "real" trap number for this vector ignoring the synchronous * versus asynchronous indicator included with our vector numbers. */ real_vector = SPARC_REAL_TRAP_NUMBER( vector ); /* * Get the current base address of the trap table and calculate a pointer * to the slot we are interested in. */ sparc_get_tbr( u32_tbr ); u32_tbr &= 0xfffff000; tbr = (CPU_Trap_table_entry *) u32_tbr; slot = &tbr[ real_vector ]; /* * Get the address of the old_handler from the trap table. * * NOTE: The old_handler returned will be bogus if it does not follow * the RTEMS model. */ #define HIGH_BITS_MASK 0xFFFFFC00 #define HIGH_BITS_SHIFT 10 #define LOW_BITS_MASK 0x000003FF if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { u32_handler = ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) | (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); *old_handler = (proc_ptr) u32_handler; } else *old_handler = 0; /* * Copy the template to the slot and then fix it. */ *slot = _CPU_Trap_slot_template; u32_handler = (unsigned32) new_handler; slot->mov_vector_l3 |= vector; slot->sethi_of_handler_to_l4 |= (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); /* need to flush icache after this !!! */ rtems_cache_invalidate_entire_instruction(); }
其中，每个中断在中断向量表中都占用4条指令，下面是rtems使用的模板，首先保存psr到l0，然后通过hi和lo跳转到handler地址，最后将vector放在l3（这是为什么？）
const CPU_Trap_table_entry _CPU_Trap_slot_template = { 0xa1480000, /* mov %psr, %l0 */ 0x29000000, /* sethi %hi(_handler), %l4 */ 0x81c52000, /* jmp %l4 + %lo(_handler) */ 0xa6102000 /* mov _vector, %l3 */ };
在_CPU_ISR_install_raw_handler时，首先获取tbr的地址，使用了如下方式，看不懂，怎么有冒号：
/* * Get and set the TBR */ #define sparc_get_tbr( _tbr ) do { (_tbr) = 0; /* to avoid unitialized warnings */ asm volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); } while ( 0 )
然后，根据vector获取中断向量表的slot。
然后，获取old handler，获取时，判断一下第一条指令是否符合模板，若符合才获取。获取方法为将第2、3条指令的跳转地址拼接起来。
然后，将slot对应的4条指令刷为模板，然后，将跳转地址更新为new handler。
该目录下，放着sparc CPU相关的东西，cpukitscorecpusparc temsscore。