红绿灯的状态机实现

module traffic(clk,rst,out,time1,time2);
input clk,rst;
output reg [5:0] out;
reg [3:0]timecont;
output reg [3:0]time1;
output reg[3:0]time2;

wire clk1h;

reg [1:0] cur_state; reg [1:0] next_state;

parameter S1 = 4'b00,
S2 = 4'b01,
S3 = 4'b10,
S4 = 4'b11;

parameter timegreen = 10,
timeyellow = 3,
timered = 5;

divodd #(12500000) CLK1H (
.clk(clk),
.rst(rst),
.clkout(clk1h));

always @ (posedge clk1h or negedge rst )
begin
if(!rst)
cur_state <= S1;
else begin
cur_state <= next_state;
end
end
always @ (cur_state or rst or timecont)
begin
if(!rst) begin
next_state <= S1;
end
else begin
case(cur_state)
S1:begin
if(timecont==0) begin
next_state <= S2;
end
else begin
next_state <= S1;
end
end

S2:begin
if(timecont==0) begin
next_state <= S3;
end
else begin
next_state <= S2;
end
end

S3:begin
if(timecont==0) begin
next_state <= S4;
end
else begin
next_state <= S3;
end
end

S4:begin
if(timecont==0) begin
next_state <= S1;
end
else begin
next_state <= S4;
end
end

default: begin
next_state <= S1;
end

endcase
end
end

always @ (posedge clk1h or negedge rst )
begin
if(!rst) begin
out <= 6'b110011;
timecont <= timegreen;
end
else begin
case(next_state)
S1:begin
out <= 6'b110011;
if(timecont == 0)
begin
timecont <= timegreen;
time1<=timegreen;
time2<=14;
end
else
begin
timecont <= timecont - 1;
time1<=time1-1;
time2<=time2-1;
end
end
S2:begin
out <= 6'b101011;
if(timecont == 0)
begin
timecont <= timeyellow;
time1<=timeyellow;
time2<=3;
end
else
begin
timecont <= timecont - 1;
time1<=time1-1;
time2<=time2-1;
end
end
S3:begin
out <= 6'b011110;
if(timecont == 0)
begin
timecont <= timered;
time1<=9;
time2<=timered;
end
else
begin
time1<=time1-1;
time2<=time2-1;
timecont <= timecont - 1;
end
end
S4:begin
out <= 6'b011101;
if(timecont == 0)
begin
time1<=3;
time2<=timeyellow;
timecont <= timeyellow;
end
else
begin
time1<=time1-1;
time2<=time2-1;
timecont <= timecont - 1;
end
end
default:begin
out <= 6'b110011;
end
endcase
end
end
endmodule