常用频率分频

module fenpin #
(parameter N=25000_000)
(clk,clr,clk0,clk1,clk2,clk3,clk4);
input clk,clr;
output clk0,clk1,clk2,clk3,clk4;
reg clk0,clk1,clk2,clk3,clk4;
reg[12:0] cnter0;
reg[4:0] cnter1,cnter2,cnter3,cnter4;
always@(posedge clk or negedge clr)
if (~clr)
cnter0<=0;
else
if (cnter0==N-1)
begin
cnter0<=0; clk0<=1'b1;
end
else
begin
cnter0<=cnter0+1; clk0<=0;//10k
end

always@(posedge clk0 or negedge clr)
if (~clr)
cnter1<=0;
else
if(cnter1==9)
begin
cnter1<=0; clk1<=1'b1;;
end
else
begin
cnter1<=cnter1+1;clk1<=0;//1k
end
always@(posedge clk1 or negedge clr)
if (~clr)
cnter2<=0;
else
if (cnter2==9)
begin
cnter2<=0; clk2<=1'b1;;
end
else
begin
cnter2<=cnter2+1;clk2<=0;//100
end
always@(posedge clk2 or negedge clr)
if (~clr)
cnter3<=0;
else
if (cnter3==9)
begin
cnter3<=0; clk3<=1'b1;;
end
else
begin
cnter3<=cnter3+1;clk3<=0;//10
end
always@(posedge clk3 or negedge clr)
if (~clr)
cnter4<=0;
else
if(cnter4==9)
begin
cnter4<=0; clk4<=1'b1;;
end
else
begin
cnter4<=cnter4+1;clk4<=0;//1
end
endmodule