`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:19:25 05/13/2014
//----------------------------------------------------------------------------------
//-- Company: Digilent Ro
//-- Engineer: xiabo
//-- Design Name: VmodCAM Reference Design 2
//-- Module Name: VmodCAM_Ref - Behavioral
//-- Project Name:
//-- Target Devices:
//-- Tool versions:
//-- Description: The design shows off the video feed from two cameras located on
//-- a VmodCAM add-on board connected to an Atlys. The video feeds are displayed on
//-- a DVI-capable flat panel at 1600x900@60Hz resolution. Each of the video feeds
//-- is written to a frame buffer port to different locations in the RAM. Switch 7
//-- can change the display from one feed to the other.
//--
//-- Dependencies:
//-- digilent VHDL library (Video, VideoTimingCtl, TWICtl, TMDSEncoder,
//-- DVITransmitter, SerializerN_1...)
//--
//-- Revision:
//-- Revision 0.01 - File Created
//-- Additional Comments:
//--
//----------------------------------------------------------------------------------
module VmodCAM_Ref #(
parameter C3_NUM_DQ_PINS = 16,
parameter C3_MEM_ADDR_WIDTH = 13,
parameter C3_MEM_BANKADDR_WIDTH = 3
)
(
output TMDS_TX_2_P ,
output TMDS_TX_2_N ,
output TMDS_TX_1_P ,
output TMDS_TX_1_N ,
output TMDS_TX_0_P ,
output TMDS_TX_0_N ,
output TMDS_TX_CLK_P ,
output TMDS_TX_CLK_N ,
input[7:0] SW_I, //: in STD_LOGIC_VECTOR(7 downto 0);
output[7:0] LED_O , //: out STD_LOGIC_VECTOR(7 downto 0);
input CLK_I , //: in STD_LOGIC;
input RESET_I , //: in STD_LOGIC;
//----------------------------------------------------------------------------------
//-- Camera Board signals
//----------------------------------------------------------------------------------
inout CAMA_SDA ,//
inout CAMA_SCL ,//
input[7:0] CAMA_D_I ,// STD_LOGIC_VECTOR (7 downto 0); -- inout Workaround for IN_TERM bug AR# 40818
input CAMA_PCLK_I ,// -- inout Workaround for IN_TERM bug AR# 40818
output CAMA_MCLK_O , // out STD_LOGIC;
input CAMA_LV_I ,// STD_LOGIC; -- inout Workaround for IN_TERM bug AR# 40818
input CAMA_FV_I ,// STD_LOGIC; -- inout Workaround for IN_TERM bug AR# 40818
output CAMA_RST_O ,//out STD_LOGIC; --Reset active LOW
output CAMA_PWDN_O ,//out STD_LOGIC; --Power-down active HIGH
output CAMX_VDDEN_O,//: out STD_LOGIC; //-- common power supply enable (can do power cycle)
inout CAMB_SDA ,//
inout CAMB_SCL ,//
input[7:0] CAMB_D_I ,// STD_LOGIC_VECTOR (7 downto 0); -- inout Workaround for IN_TERM bug AR# 40818
input CAMB_PCLK_I ,// -- inout Workaround for IN_TERM bug AR# 40818
output CAMB_MCLK_O ,//: out STD_LOGIC;
input CAMB_LV_I ,// STD_LOGIC; -- inout Workaround for IN_TERM bug AR# 40818
input CAMB_FV_I ,// STD_LOGIC; -- inout Workaround for IN_TERM bug AR# 40818
output CAMB_RST_O ,//: out STD_LOGIC; --Reset active LOW
output CAMB_PWDN_O,// : out STD_LOGIC; --Power-down active HIGH
//----------------------------------------------------------------------------------
//-- DDR2 Interface
//----------------------------------------------------------------------------------
inout [C3_NUM_DQ_PINS-1 : 0] mcb3_dram_dq ,// inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
output[C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a ,// out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
output[C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba ,// out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
output mcb3_dram_ras_n ,// out std_logic;
output mcb3_dram_cas_n ,// out std_logic;
output mcb3_dram_we_n ,// out std_logic;
output mcb3_dram_odt ,// out std_logic;
output mcb3_dram_cke ,// out std_logic;
output mcb3_dram_dm ,// out std_logic;
output mcb3_dram_udqs ,// inout std_logic;
inout mcb3_dram_udqs_n ,// inout std_logic;
inout mcb3_rzq ,// inout std_logic;
inout mcb3_zio ,// inout std_logic;
output mcb3_dram_udm ,// out std_logic;
inout mcb3_dram_dqs ,// inout std_logic;
inout mcb3_dram_dqs_n ,// inout std_logic;
output mcb3_dram_ck ,// out std_logic;
output mcb3_dram_ck_n // out std_logic
);
//----------------------------------------------------------------------------------
//-- System unit define
//-- wire
//----------------------------------------------------------------------------------
wire SysClk, PClk, PClkX2, SysRst, SerClk, SerStb ;//: std_logic;
wire MSel; //: std_logic_vector(0 downto 0);
wire VtcHs, VtcVs, VtcVde, VtcRst ;//: std_logic;
wire VtcHCnt, VtcVCnt ;//: NATURAL;
wire CamClk, CamClk_180, CamAPClk, CamBPClk, CamADV, CamBDV, CamAVddEn, CamBVddEn ;//: std_logic;
wire [15:0] CamAD;
wire [15:0] CamBD ;// std_logic_vector(15 downto 0);
wire dummy_t, int_CAMA_PCLK_I, int_CAMA_FV_I, int_CAMA_LV_I,int_CAMB_PCLK_I, int_CAMB_FV_I, int_CAMB_LV_I; //: std_logic;
wire [7:0] int_CAMA_D_I;
wire [7:0] int_CAMB_D_I; // std_logic_vector(7 downto 0);
wire ddr2clk_2x, ddr2clk_2x_180, mcb_drp_clk, pll_ce_0, pll_ce_90, pll_lock, async_rst ;//: std_logic;
wire FbRdy, FbRdEn, FbRdRst, FbRdClk; //: std_logic;
wire [15:0] FbRdData ;//: std_logic_vector(16-1 downto 0);
wire FbWrARst, FbWrBRst, int_FVA, int_FVB ;//: std_logic;
assign LED_O = {VtcHs , VtcHs , VtcVde , async_rst , MSel , 3'b000};
//----------------------------------------------------------------------------------
//-- System Control Unit
//-- This component provides a System Clock, a Synchronous Reset and other signals
//-- needed for the 40:4 serialization:
//-- - Serialization clock (5x System Clock)
//-- - Serialization strobe
//-- - 2x Pixel Clock
//----------------------------------------------------------------------------------
SysCon Inst_SysCon(
.CLK_I ( CLK_I),
.CLK_O ( open),
.RSTN_I ( RESET_I),
.SW_I ( SW_I),
.SW_O ( open),
.RSEL_O ( open), //--resolution selector synchronized with PClk
.MSEL_O ( MSel), //--mode selector synchronized with PClk
.CAMCLK_O ( CamClk),
.CAMCLK_180_O ( CamClk_180),
.PCLK_O ( PClk),
.PCLK_X2_O ( PClkX2),
.PCLK_X10_O ( SerClk),
.SERDESSTROBE_O ( SerStb),
.DDR2CLK_2X_O ( DDR2Clk_2x),
.DDR2CLK_2X_180_O ( DDR2Clk_2x_180),
.MCB_DRP_CLK_O ( mcb_drp_clk),
.PLL_CE_0_O ( pll_ce_0),
.PLL_CE_90_O ( pll_ce_90),
.PLL_LOCK ( pll_lock),
.ASYNC_RST ( async_rst)
);
//----------------------------------------------------------------------------------
//-- Video Timing Controller
//-- Generates horizontal and vertical sync and video data enable signals.
//----------------------------------------------------------------------------------
VideoTimingCtl Inst_VideoTimingCtl (
.PCLK_I ( PClk),
.RSEL_I ( R1600_900P),// --this project supports only 1600x900
.RST_I ( VtcRst),
.VDE_O ( VtcVde),
.HS_O ( VtcHs),
.VS_O ( VtcVs),
.HCNT_O ( VtcHCnt),
.VCNT_O ( VtcVCnt)
);
assign VtcRst = async_rst | (!FbRdy);
//----------------------------------------------------------------------------------
//-- Frame Buffer
//----------------------------------------------------------------------------------
parameter DEBUG_EN = 0;
parameter COLORDEPTH = 16;
FBCtl #(
.DEBUG_EN(DEBUG_EN),
.COLORDEPTH(COLORDEPTH)
)
Inst_FBCtl(
.RDY_O ( FbRdy),
.ENC ( FbRdEn),
.RSTC_I ( FbRdRst),
.DOC ( FbRdData),
.CLKC ( FbRdClk),
.RD_MODE ( MSel),
.ENA ( CamADV),
.RSTA_I ( FbWrARst),
.DIA ( CamAD),
.CLKA ( CamAPClk),
.ENB ( CamBDV),
.RSTB_I ( FbWrBRst),
.DIB ( CamBD),
.CLKB ( CamBPClk),
.ddr2clk_2x ( DDR2Clk_2x),
.ddr2clk_2x_180 ( DDR2Clk_2x_180),
.pll_ce_0 ( pll_ce_0),
.pll_ce_90 ( pll_ce_90),
.pll_lock ( pll_lock),
.async_rst ( async_rst),
.mcb_drp_clk ( mcb_drp_clk),
.mcb3_dram_dq ( mcb3_dram_dq),
.mcb3_dram_a ( mcb3_dram_a),
.mcb3_dram_ba ( mcb3_dram_ba),
.mcb3_dram_ras_n ( mcb3_dram_ras_n),
.mcb3_dram_cas_n ( mcb3_dram_cas_n),
.mcb3_dram_we_n ( mcb3_dram_we_n),
.mcb3_dram_odt ( mcb3_dram_odt),
.mcb3_dram_cke ( mcb3_dram_cke),
.mcb3_dram_dm ( mcb3_dram_dm),
.mcb3_dram_udqs ( mcb3_dram_udqs),
.mcb3_dram_udqs_n ( mcb3_dram_udqs_n),
.mcb3_rzq ( mcb3_rzq),
.mcb3_zio ( mcb3_zio),
.mcb3_dram_udm ( mcb3_dram_udm),
.mcb3_dram_dqs ( mcb3_dram_dqs),
.mcb3_dram_dqs_n ( mcb3_dram_dqs_n),
.mcb3_dram_ck ( mcb3_dram_ck),
.mcb3_dram_ck_n ( mcb3_dram_ck_n)
);
assign FbRdEn = VtcVde;
assign FbRdRst = async_rst;
assign FbRdClk = PClk;
//--Register FV signal to meet timing for FbWrXRst
InputSync Inst_InputSync_FVA(
.D_I ( int_CAMA_FV_I),
.D_O ( int_FVA),
.CLK_I ( CamAPClk)
);
InputSync Inst_InputSync_FVB(
.D_I ( int_CAMB_FV_I),
.D_O ( int_FVB),
.CLK_I ( CamBPClk)
);
assign FbWrARst = async_rst | ( !int_FVA);
assign FbWrBRst = async_rst | ( !int_FVB);
//----------------------------------------------------------------------------------
//-- DVI Transmitter
//----------------------------------------------------------------------------------
wire [7:0] FbRdData_Red;
wire [7:0] FbRdData_Green;
wire [7:0] FbRdData_Blue;
assign FbRdData_Red = {FbRdData[15 : 11],3'b000};
assign FbRdData_Green = {FbRdData[10 : 5] ,2'b00 };
assign FbRdData_Blue = {FbRdData[4 : 0] ,3'b000};
DVITransmitter Inst_DVITransmitter(
// .RED_I ( FbRdData[15 : 11] & "000"),
// .GREEN_I ( FbRdData[10 : 5] & "00"),
// .BLUE_I ( FbRdData[4 : 0] & "000"),
.RED_I ( FbRdData_Red),
.GREEN_I ( FbRdData_Green),
.BLUE_I ( FbRdData_Blue),
.HS_I ( VtcHs),
.VS_I ( VtcVs),
.VDE_I ( VtcVde),
.PCLK_I ( PClk),
.PCLK_X2_I ( PClkX2),
.SERCLK_I ( SerClk),
.SERSTB_I ( SerStb),
.TMDS_TX_2_P ( TMDS_TX_2_P),
.TMDS_TX_2_N ( TMDS_TX_2_N),
.TMDS_TX_1_P ( TMDS_TX_1_P),
.TMDS_TX_1_N ( TMDS_TX_1_N),
.TMDS_TX_0_P ( TMDS_TX_0_P),
.TMDS_TX_0_N ( TMDS_TX_0_N),
.TMDS_TX_CLK_P ( TMDS_TX_CLK_P),
.TMDS_TX_CLK_N ( TMDS_TX_CLK_N)
);
//----------------------------------------------------------------------------------
//-- Camera A Controller
//----------------------------------------------------------------------------------
camctl Inst_camctlA(
.D_O ( CamAD),
.PCLK_O ( CamAPClk),
.DV_O ( CamADV),
.RST_I ( async_rst),
.CLK ( CamClk),
.CLK_180 ( CamClk_180),
.SDA ( CAMA_SDA),
.SCL ( CAMA_SCL),
.D_I ( CAMA_D_I),
.PCLK_I ( CAMA_PCLK_I),
.MCLK_O ( CAMA_MCLK_O),
.LV_I ( CAMA_LV_I),
.FV_I ( CAMA_FV_I),
.RST_O ( CAMA_RST_O),
.PWDN_O ( CAMA_PWDN_O),
.VDDEN_O ( CamAVddEn)
);
//----------------------------------------------------------------------------------
//-- Camera B Controller
//----------------------------------------------------------------------------------
camctl Inst_camctlB(
.D_O ( CamBD),
.PCLK_O ( CamBPClk),
.DV_O ( CamBDV),
.RST_I ( async_rst),
.CLK ( CamClk),
.CLK_180 ( CamClk_180),
.SDA ( CAMB_SDA),
.SCL ( CAMB_SCL),
.D_I ( CAMB_D_I),
.PCLK_I ( CAMB_PCLK_I),
.MCLK_O ( CAMB_MCLK_O),
.LV_I ( CAMB_LV_I),
.FV_I ( CAMB_FV_I),
.RST_O ( CAMB_RST_O),
.PWDN_O ( CAMB_PWDN_O),
.VDDEN_O ( CamBVddEn)
);
assign CAMX_VDDEN_O = CamAVddEn && CamBVddEn;
endmodule
VmodCam top verilog
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