一、DM9000 网卡硬件描述
DM9000是开发板采用的网络芯片，是一个高度集成且功耗很低的告诉网络控制器，可以和 CPU 直连，支持 10/100MB 以太网连接，芯片内部自带 4KB 双字节的 SRAM （3KB用来发送， 13KB用来接收）。针对不同的处理器，接口支持 8 位、16 位和 32位。DM9000一般直接挂在外面的内存总线上。
二、DM9000网卡驱动设计分析
DM9000网卡驱动位于内核源代码的 drivers/net/ethernet/davicom/dm9000.c 中，它基于平台驱动架构，其核心工作是实现了前文所述 net_device 结构体中的 hard_start_xmit()、open()、stop()、set_multicast_list()、do_ioctl()、tx_timeout()等成员函数，并借助中断辅助进行网络数据包的收发，另外它也实现了 ethtool_ops 中的成员函数。
1 #include <linux/module.h> 2 #include <linux/ioport.h> 3 #include <linux/netdevice.h> 4 #include <linux/etherdevice.h> 5 #include <linux/interrupt.h> 6 #include <linux/skbuff.h> 7 #include <linux/spinlock.h> 8 #include <linux/crc32.h> 9 #include <linux/mii.h> 10 #include <linux/of.h> 11 #include <linux/of_net.h> 12 #include <linux/ethtool.h> 13 #include <linux/dm9000.h> 14 #include <linux/delay.h> 15 #include <linux/platform_device.h> 16 #include <linux/irq.h> 17 #include <linux/slab.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/gpio.h> 20 #include <linux/of_gpio.h> 21 22 #include <asm/delay.h> 23 #include <asm/irq.h> 24 #include <asm/io.h> 25 26 #include "dm9000.h" 27 28 /* Board/System/Debug information/definition ---------------- */ 29 30 #define DM9000_PHY 0x40 /* PHY address 0x01 */ 31 32 #define CARDNAME "dm9000" 33 #define DRV_VERSION "1.31" 34 35 /* 36 * Transmit timeout, default 5 seconds. 37 */ 38 static int watchdog = 5000; 39 module_param(watchdog, int, 0400); 40 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 41 42 /* 43 * Debug messages level 44 */ 45 static int debug; 46 module_param(debug, int, 0644); 47 MODULE_PARM_DESC(debug, "dm9000 debug level (0-4)"); 48 49 /* DM9000 register address locking. 50 * 51 * The DM9000 uses an address register to control where data written 52 * to the data register goes. This means that the address register 53 * must be preserved over interrupts or similar calls. 54 * 55 * During interrupt and other critical calls, a spinlock is used to 56 * protect the system, but the calls themselves save the address 57 * in the address register in case they are interrupting another 58 * access to the device. 59 * 60 * For general accesses a lock is provided so that calls which are 61 * allowed to sleep are serialised so that the address register does 62 * not need to be saved. This lock also serves to serialise access 63 * to the EEPROM and PHY access registers which are shared between 64 * these two devices. 65 */ 66 67 /* The driver supports the original DM9000E, and now the two newer 68 * devices, DM9000A and DM9000B. 69 */ 70 71 enum dm9000_type { 72 TYPE_DM9000E, /* original DM9000 */ 73 TYPE_DM9000A, 74 TYPE_DM9000B 75 }; 76 77 /* Structure/enum declaration ------------------------------- */ 78 struct board_info { 79 80 void __iomem *io_addr; /* Register I/O base address */ 81 void __iomem *io_data; /* Data I/O address */ 82 u16 irq; /* IRQ */ 83 84 u16 tx_pkt_cnt; 85 u16 queue_pkt_len; 86 u16 queue_start_addr; 87 u16 queue_ip_summed; 88 u16 dbug_cnt; 89 u8 io_mode; /* 0:word, 2:byte */ 90 u8 phy_addr; 91 u8 imr_all; 92 93 unsigned int flags; 94 unsigned int in_timeout:1; 95 unsigned int in_suspend:1; 96 unsigned int wake_supported:1; 97 98 enum dm9000_type type; 99 100 void (*inblk)(void __iomem *port, void *data, int length); 101 void (*outblk)(void __iomem *port, void *data, int length); 102 void (*dumpblk)(void __iomem *port, int length); 103 104 struct device *dev; /* parent device */ 105 106 struct resource *addr_res; /* resources found */ 107 struct resource *data_res; 108 struct resource *addr_req; /* resources requested */ 109 struct resource *data_req; 110 struct resource *irq_res; 111 112 int irq_wake; 113 114 struct mutex addr_lock; /* phy and eeprom access lock */ 115 116 struct delayed_work phy_poll; 117 struct net_device *ndev; 118 119 spinlock_t lock; 120 121 struct mii_if_info mii; 122 u32 msg_enable; 123 u32 wake_state; 124 125 int ip_summed; 126 }; 127 128 /* debug code */ 129 130 #define dm9000_dbg(db, lev, msg...) do { 131 if ((lev) < debug) { 132 dev_dbg(db->dev, msg); 133 } 134 } while (0) 135 136 static inline struct board_info *to_dm9000_board(struct net_device *dev) 137 { 138 return netdev_priv(dev); 139 } 140 141 /* DM9000 network board routine ---------------------------- */ 142 143 /* 144 * Read a byte from I/O port 145 */ 146 static u8 147 ior(struct board_info *db, int reg) 148 { 149 writeb(reg, db->io_addr); 150 return readb(db->io_data); 151 } 152 153 /* 154 * Write a byte to I/O port 155 */ 156 157 static void 158 iow(struct board_info *db, int reg, int value) 159 { 160 writeb(reg, db->io_addr); 161 writeb(value, db->io_data); 162 } 163 164 static void 165 dm9000_reset(struct board_info *db) 166 { 167 dev_dbg(db->dev, "resetting device "); 168 169 /* Reset DM9000, see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 170 * The essential point is that we have to do a double reset, and the 171 * instruction is to set LBK into MAC internal loopback mode. 172 */ 173 iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK); 174 udelay(100); /* Application note says at least 20 us */ 175 if (ior(db, DM9000_NCR) & 1) 176 dev_err(db->dev, "dm9000 did not respond to first reset "); 177 178 iow(db, DM9000_NCR, 0); 179 iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK); 180 udelay(100); 181 if (ior(db, DM9000_NCR) & 1) 182 dev_err(db->dev, "dm9000 did not respond to second reset "); 183 } 184 185 /* routines for sending block to chip */ 186 187 static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) 188 { 189 iowrite8_rep(reg, data, count); 190 } 191 192 static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) 193 { 194 iowrite16_rep(reg, data, (count+1) >> 1); 195 } 196 197 static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) 198 { 199 iowrite32_rep(reg, data, (count+3) >> 2); 200 } 201 202 /* input block from chip to memory */ 203 204 static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) 205 { 206 ioread8_rep(reg, data, count); 207 } 208 209 210 static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) 211 { 212 ioread16_rep(reg, data, (count+1) >> 1); 213 } 214 215 static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) 216 { 217 ioread32_rep(reg, data, (count+3) >> 2); 218 } 219 220 /* dump block from chip to null */ 221 222 static void dm9000_dumpblk_8bit(void __iomem *reg, int count) 223 { 224 int i; 225 int tmp; 226 227 for (i = 0; i < count; i++) 228 tmp = readb(reg); 229 } 230 231 static void dm9000_dumpblk_16bit(void __iomem *reg, int count) 232 { 233 int i; 234 int tmp; 235 236 count = (count + 1) >> 1; 237 238 for (i = 0; i < count; i++) 239 tmp = readw(reg); 240 } 241 242 static void dm9000_dumpblk_32bit(void __iomem *reg, int count) 243 { 244 int i; 245 int tmp; 246 247 count = (count + 3) >> 2; 248 249 for (i = 0; i < count; i++) 250 tmp = readl(reg); 251 } 252 253 /* 254 * Sleep, either by using msleep() or if we are suspending, then 255 * use mdelay() to sleep. 256 */ 257 static void dm9000_msleep(struct board_info *db, unsigned int ms) 258 { 259 if (db->in_suspend || db->in_timeout) 260 mdelay(ms); 261 else 262 msleep(ms); 263 } 264 265 /* Read a word from phyxcer */ 266 static int 267 dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) 268 { 269 struct board_info *db = netdev_priv(dev); 270 unsigned long flags; 271 unsigned int reg_save; 272 int ret; 273 274 mutex_lock(&db->addr_lock); 275 276 spin_lock_irqsave(&db->lock, flags); 277 278 /* Save previous register address */ 279 reg_save = readb(db->io_addr); 280 281 /* Fill the phyxcer register into REG_0C */ 282 iow(db, DM9000_EPAR, DM9000_PHY | reg); 283 284 /* Issue phyxcer read command */ 285 iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); 286 287 writeb(reg_save, db->io_addr); 288 spin_unlock_irqrestore(&db->lock, flags); 289 290 dm9000_msleep(db, 1); /* Wait read complete */ 291 292 spin_lock_irqsave(&db->lock, flags); 293 reg_save = readb(db->io_addr); 294 295 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ 296 297 /* The read data keeps on REG_0D & REG_0E */ 298 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); 299 300 /* restore the previous address */ 301 writeb(reg_save, db->io_addr); 302 spin_unlock_irqrestore(&db->lock, flags); 303 304 mutex_unlock(&db->addr_lock); 305 306 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x ", reg, ret); 307 return ret; 308 } 309 310 /* Write a word to phyxcer */ 311 static void 312 dm9000_phy_write(struct net_device *dev, 313 int phyaddr_unused, int reg, int value) 314 { 315 struct board_info *db = netdev_priv(dev); 316 unsigned long flags; 317 unsigned long reg_save; 318 319 dm9000_dbg(db, 5, "phy_write[%02x] = %04x ", reg, value); 320 if (!db->in_timeout) 321 mutex_lock(&db->addr_lock); 322 323 spin_lock_irqsave(&db->lock, flags); 324 325 /* Save previous register address */ 326 reg_save = readb(db->io_addr); 327 328 /* Fill the phyxcer register into REG_0C */ 329 iow(db, DM9000_EPAR, DM9000_PHY | reg); 330 331 /* Fill the written data into REG_0D & REG_0E */ 332 iow(db, DM9000_EPDRL, value); 333 iow(db, DM9000_EPDRH, value >> 8); 334 335 /* Issue phyxcer write command */ 336 iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); 337 338 writeb(reg_save, db->io_addr); 339 spin_unlock_irqrestore(&db->lock, flags); 340 341 dm9000_msleep(db, 1); /* Wait write complete */ 342 343 spin_lock_irqsave(&db->lock, flags); 344 reg_save = readb(db->io_addr); 345 346 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ 347 348 /* restore the previous address */ 349 writeb(reg_save, db->io_addr); 350 351 spin_unlock_irqrestore(&db->lock, flags); 352 if (!db->in_timeout) 353 mutex_unlock(&db->addr_lock); 354 } 355 356 /* dm9000_set_io 357 * 358 * select the specified set of io routines to use with the 359 * device 360 */ 361 362 static void dm9000_set_io(struct board_info *db, int byte_width) 363 { 364 /* use the size of the data resource to work out what IO 365 * routines we want to use 366 */ 367 368 switch (byte_width) { 369 case 1: 370 db->dumpblk = dm9000_dumpblk_8bit; 371 db->outblk = dm9000_outblk_8bit; 372 db->inblk = dm9000_inblk_8bit; 373 break; 374 375 376 case 3: 377 dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit "); 378 case 2: 379 db->dumpblk = dm9000_dumpblk_16bit; 380 db->outblk = dm9000_outblk_16bit; 381 db->inblk = dm9000_inblk_16bit; 382 break; 383 384 case 4: 385 default: 386 db->dumpblk = dm9000_dumpblk_32bit; 387 db->outblk = dm9000_outblk_32bit; 388 db->inblk = dm9000_inblk_32bit; 389 break; 390 } 391 } 392 393 static void dm9000_schedule_poll(struct board_info *db) 394 { 395 if (db->type == TYPE_DM9000E) 396 schedule_delayed_work(&db->phy_poll, HZ * 2); 397 } 398 399 static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 400 { 401 struct board_info *dm = to_dm9000_board(dev); 402 403 if (!netif_running(dev)) 404 return -EINVAL; 405 406 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); 407 } 408 409 static unsigned int 410 dm9000_read_locked(struct board_info *db, int reg) 411 { 412 unsigned long flags; 413 unsigned int ret; 414 415 spin_lock_irqsave(&db->lock, flags); 416 ret = ior(db, reg); 417 spin_unlock_irqrestore(&db->lock, flags); 418 419 return ret; 420 } 421 422 static int dm9000_wait_eeprom(struct board_info *db) 423 { 424 unsigned int status; 425 int timeout = 8; /* wait max 8msec */ 426 427 /* The DM9000 data sheets say we should be able to 428 * poll the ERRE bit in EPCR to wait for the EEPROM 429 * operation. From testing several chips, this bit 430 * does not seem to work. 431 * 432 * We attempt to use the bit, but fall back to the 433 * timeout (which is why we do not return an error 434 * on expiry) to say that the EEPROM operation has 435 * completed. 436 */ 437 438 while (1) { 439 status = dm9000_read_locked(db, DM9000_EPCR); 440 441 if ((status & EPCR_ERRE) == 0) 442 break; 443 444 msleep(1); 445 446 if (timeout-- < 0) { 447 dev_dbg(db->dev, "timeout waiting EEPROM "); 448 break; 449 } 450 } 451 452 return 0; 453 } 454 455 /* 456 * Read a word data from EEPROM 457 */ 458 static void 459 dm9000_read_eeprom(struct board_info *db, int offset, u8 *to) 460 { 461 unsigned long flags; 462 463 if (db->flags & DM9000_PLATF_NO_EEPROM) { 464 to[0] = 0xff; 465 to[1] = 0xff; 466 return; 467 } 468 469 mutex_lock(&db->addr_lock); 470 471 spin_lock_irqsave(&db->lock, flags); 472 473 iow(db, DM9000_EPAR, offset); 474 iow(db, DM9000_EPCR, EPCR_ERPRR); 475 476 spin_unlock_irqrestore(&db->lock, flags); 477 478 dm9000_wait_eeprom(db); 479 480 /* delay for at-least 150uS */ 481 msleep(1); 482 483 spin_lock_irqsave(&db->lock, flags); 484 485 iow(db, DM9000_EPCR, 0x0); 486 487 to[0] = ior(db, DM9000_EPDRL); 488 to[1] = ior(db, DM9000_EPDRH); 489 490 spin_unlock_irqrestore(&db->lock, flags); 491 492 mutex_unlock(&db->addr_lock); 493 } 494 495 /* 496 * Write a word data to SROM 497 */ 498 static void 499 dm9000_write_eeprom(struct board_info *db, int offset, u8 *data) 500 { 501 unsigned long flags; 502 503 if (db->flags & DM9000_PLATF_NO_EEPROM) 504 return; 505 506 mutex_lock(&db->addr_lock); 507 508 spin_lock_irqsave(&db->lock, flags); 509 iow(db, DM9000_EPAR, offset); 510 iow(db, DM9000_EPDRH, data[1]); 511 iow(db, DM9000_EPDRL, data[0]); 512 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); 513 spin_unlock_irqrestore(&db->lock, flags); 514 515 dm9000_wait_eeprom(db); 516 517 mdelay(1); /* wait at least 150uS to clear */ 518 519 spin_lock_irqsave(&db->lock, flags); 520 iow(db, DM9000_EPCR, 0); 521 spin_unlock_irqrestore(&db->lock, flags); 522 523 mutex_unlock(&db->addr_lock); 524 } 525 526 /* ethtool ops */ 527 528 static void dm9000_get_drvinfo(struct net_device *dev, 529 struct ethtool_drvinfo *info) 530 { 531 struct board_info *dm = to_dm9000_board(dev); 532 533 strlcpy(info->driver, CARDNAME, sizeof(info->driver)); 534 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 535 strlcpy(info->bus_info, to_platform_device(dm->dev)->name, 536 sizeof(info->bus_info)); 537 } 538 539 static u32 dm9000_get_msglevel(struct net_device *dev) 540 { 541 struct board_info *dm = to_dm9000_board(dev); 542 543 return dm->msg_enable; 544 } 545 546 static void dm9000_set_msglevel(struct net_device *dev, u32 value) 547 { 548 struct board_info *dm = to_dm9000_board(dev); 549 550 dm->msg_enable = value; 551 } 552 553 static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 554 { 555 struct board_info *dm = to_dm9000_board(dev); 556 557 mii_ethtool_gset(&dm->mii, cmd); 558 return 0; 559 } 560 561 static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 562 { 563 struct board_info *dm = to_dm9000_board(dev); 564 565 return mii_ethtool_sset(&dm->mii, cmd); 566 } 567 568 static int dm9000_nway_reset(struct net_device *dev) 569 { 570 struct board_info *dm = to_dm9000_board(dev); 571 return mii_nway_restart(&dm->mii); 572 } 573 574 static int dm9000_set_features(struct net_device *dev, 575 netdev_features_t features) 576 { 577 struct board_info *dm = to_dm9000_board(dev); 578 netdev_features_t changed = dev->features ^ features; 579 unsigned long flags; 580 581 if (!(changed & NETIF_F_RXCSUM)) 582 return 0; 583 584 spin_lock_irqsave(&dm->lock, flags); 585 iow(dm, DM9000_RCSR, (features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0); 586 spin_unlock_irqrestore(&dm->lock, flags); 587 588 return 0; 589 } 590 591 static u32 dm9000_get_link(struct net_device *dev) 592 { 593 struct board_info *dm = to_dm9000_board(dev); 594 u32 ret; 595 596 if (dm->flags & DM9000_PLATF_EXT_PHY) 597 ret = mii_link_ok(&dm->mii); 598 else 599 ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0; 600 601 return ret; 602 } 603 604 #define DM_EEPROM_MAGIC (0x444D394B) 605 606 static int dm9000_get_eeprom_len(struct net_device *dev) 607 { 608 return 128; 609 } 610 611 static int dm9000_get_eeprom(struct net_device *dev, 612 struct ethtool_eeprom *ee, u8 *data) 613 { 614 struct board_info *dm = to_dm9000_board(dev); 615 int offset = ee->offset; 616 int len = ee->len; 617 int i; 618 619 /* EEPROM access is aligned to two bytes */ 620 621 if ((len & 1) != 0 || (offset & 1) != 0) 622 return -EINVAL; 623 624 if (dm->flags & DM9000_PLATF_NO_EEPROM) 625 return -ENOENT; 626 627 ee->magic = DM_EEPROM_MAGIC; 628 629 for (i = 0; i < len; i += 2) 630 dm9000_read_eeprom(dm, (offset + i) / 2, data + i); 631 632 return 0; 633 } 634 635 static int dm9000_set_eeprom(struct net_device *dev, 636 struct ethtool_eeprom *ee, u8 *data) 637 { 638 struct board_info *dm = to_dm9000_board(dev); 639 int offset = ee->offset; 640 int len = ee->len; 641 int done; 642 643 /* EEPROM access is aligned to two bytes */ 644 645 if (dm->flags & DM9000_PLATF_NO_EEPROM) 646 return -ENOENT; 647 648 if (ee->magic != DM_EEPROM_MAGIC) 649 return -EINVAL; 650 651 while (len > 0) { 652 if (len & 1 || offset & 1) { 653 int which = offset & 1; 654 u8 tmp[2]; 655 656 dm9000_read_eeprom(dm, offset / 2, tmp); 657 tmp[which] = *data; 658 dm9000_write_eeprom(dm, offset / 2, tmp); 659 660 done = 1; 661 } else { 662 dm9000_write_eeprom(dm, offset / 2, data); 663 done = 2; 664 } 665 666 data += done; 667 offset += done; 668 len -= done; 669 } 670 671 return 0; 672 } 673 674 static void dm9000_get_wol(struct net_device *dev, struct ethtool_wolinfo *w) 675 { 676 struct board_info *dm = to_dm9000_board(dev); 677 678 memset(w, 0, sizeof(struct ethtool_wolinfo)); 679 680 /* note, we could probably support wake-phy too */ 681 w->supported = dm->wake_supported ? WAKE_MAGIC : 0; 682 w->wolopts = dm->wake_state; 683 } 684 685 static int dm9000_set_wol(struct net_device *dev, struct ethtool_wolinfo *w) 686 { 687 struct board_info *dm = to_dm9000_board(dev); 688 unsigned long flags; 689 u32 opts = w->wolopts; 690 u32 wcr = 0; 691 692 if (!dm->wake_supported) 693 return -EOPNOTSUPP; 694 695 if (opts & ~WAKE_MAGIC) 696 return -EINVAL; 697 698 if (opts & WAKE_MAGIC) 699 wcr |= WCR_MAGICEN; 700 701 mutex_lock(&dm->addr_lock); 702 703 spin_lock_irqsave(&dm->lock, flags); 704 iow(dm, DM9000_WCR, wcr); 705 spin_unlock_irqrestore(&dm->lock, flags); 706 707 mutex_unlock(&dm->addr_lock); 708 709 if (dm->wake_state != opts) { 710 /* change in wol state, update IRQ state */ 711 712 if (!dm->wake_state) 713 irq_set_irq_wake(dm->irq_wake, 1); 714 else if (dm->wake_state && !opts) 715 irq_set_irq_wake(dm->irq_wake, 0); 716 } 717 718 dm->wake_state = opts; 719 return 0; 720 } 721 722 static const struct ethtool_ops dm9000_ethtool_ops = { 723 .get_drvinfo = dm9000_get_drvinfo, 724 .get_settings = dm9000_get_settings, 725 .set_settings = dm9000_set_settings, 726 .get_msglevel = dm9000_get_msglevel, 727 .set_msglevel = dm9000_set_msglevel, 728 .nway_reset = dm9000_nway_reset, 729 .get_link = dm9000_get_link, 730 .get_wol = dm9000_get_wol, 731 .set_wol = dm9000_set_wol, 732 .get_eeprom_len = dm9000_get_eeprom_len, 733 .get_eeprom = dm9000_get_eeprom, 734 .set_eeprom = dm9000_set_eeprom, 735 }; 736 737 static void dm9000_show_carrier(struct board_info *db, 738 unsigned carrier, unsigned nsr) 739 { 740 int lpa; 741 struct net_device *ndev = db->ndev; 742 struct mii_if_info *mii = &db->mii; 743 unsigned ncr = dm9000_read_locked(db, DM9000_NCR); 744 745 if (carrier) { 746 lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA); 747 dev_info(db->dev, 748 "%s: link up, %dMbps, %s-duplex, lpa 0x%04X ", 749 ndev->name, (nsr & NSR_SPEED) ? 10 : 100, 750 (ncr & NCR_FDX) ? "full" : "half", lpa); 751 } else { 752 dev_info(db->dev, "%s: link down ", ndev->name); 753 } 754 } 755 756 static void 757 dm9000_poll_work(struct work_struct *w) 758 { 759 struct delayed_work *dw = to_delayed_work(w); 760 struct board_info *db = container_of(dw, struct board_info, phy_poll); 761 struct net_device *ndev = db->ndev; 762 763 if (db->flags & DM9000_PLATF_SIMPLE_PHY && 764 !(db->flags & DM9000_PLATF_EXT_PHY)) { 765 unsigned nsr = dm9000_read_locked(db, DM9000_NSR); 766 unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0; 767 unsigned new_carrier; 768 769 new_carrier = (nsr & NSR_LINKST) ? 1 : 0; 770 771 if (old_carrier != new_carrier) { 772 if (netif_msg_link(db)) 773 dm9000_show_carrier(db, new_carrier, nsr); 774 775 if (!new_carrier) 776 netif_carrier_off(ndev); 777 else 778 netif_carrier_on(ndev); 779 } 780 } else 781 mii_check_media(&db->mii, netif_msg_link(db), 0); 782 783 if (netif_running(ndev)) 784 dm9000_schedule_poll(db); 785 } 786 787 /* dm9000_release_board 788 * 789 * release a board, and any mapped resources 790 */ 791 792 static void 793 dm9000_release_board(struct platform_device *pdev, struct board_info *db) 794 { 795 /* unmap our resources */ 796 797 iounmap(db->io_addr); 798 iounmap(db->io_data); 799 800 /* release the resources */ 801 802 if (db->data_req) 803 release_resource(db->data_req); 804 kfree(db->data_req); 805 806 if (db->addr_req) 807 release_resource(db->addr_req); 808 kfree(db->addr_req); 809 } 810 811 static unsigned char dm9000_type_to_char(enum dm9000_type type) 812 { 813 switch (type) { 814 case TYPE_DM9000E: return 'e'; 815 case TYPE_DM9000A: return 'a'; 816 case TYPE_DM9000B: return 'b'; 817 } 818 819 return '?'; 820 } 821 822 /* 823 * Set DM9000 multicast address 824 */ 825 static void 826 dm9000_hash_table_unlocked(struct net_device *dev) 827 { 828 struct board_info *db = netdev_priv(dev); 829 struct netdev_hw_addr *ha; 830 int i, oft; 831 u32 hash_val; 832 u16 hash_table[4] = { 0, 0, 0, 0x8000 }; /* broadcast address */ 833 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; 834 835 dm9000_dbg(db, 1, "entering %s ", __func__); 836 837 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) 838 iow(db, oft, dev->dev_addr[i]); 839 840 if (dev->flags & IFF_PROMISC) 841 rcr |= RCR_PRMSC; 842 843 if (dev->flags & IFF_ALLMULTI) 844 rcr |= RCR_ALL; 845 846 /* the multicast address in Hash Table : 64 bits */ 847 netdev_for_each_mc_addr(ha, dev) { 848 hash_val = ether_crc_le(6, ha->addr) & 0x3f; 849 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); 850 } 851 852 /* Write the hash table to MAC MD table */ 853 for (i = 0, oft = DM9000_MAR; i < 4; i++) { 854 iow(db, oft++, hash_table[i]); 855 iow(db, oft++, hash_table[i] >> 8); 856 } 857 858 iow(db, DM9000_RCR, rcr); 859 } 860 861 static void 862 dm9000_hash_table(struct net_device *dev) 863 { 864 struct board_info *db = netdev_priv(dev); 865 unsigned long flags; 866 867 spin_lock_irqsave(&db->lock, flags); 868 dm9000_hash_table_unlocked(dev); 869 spin_unlock_irqrestore(&db->lock, flags); 870 } 871 872 static void 873 dm9000_mask_interrupts(struct board_info *db) 874 { 875 iow(db, DM9000_IMR, IMR_PAR); 876 } 877 878 static void 879 dm9000_unmask_interrupts(struct board_info *db) 880 { 881 iow(db, DM9000_IMR, db->imr_all); 882 } 883 884 /* 885 * Initialize dm9000 board 886 */ 887 static void 888 dm9000_init_dm9000(struct net_device *dev) 889 { 890 struct board_info *db = netdev_priv(dev); 891 unsigned int imr; 892 unsigned int ncr; 893 894 dm9000_dbg(db, 1, "entering %s ", __func__); 895 896 dm9000_reset(db); 897 dm9000_mask_interrupts(db); 898 899 /* I/O mode */ 900 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ 901 902 /* Checksum mode */ 903 if (dev->hw_features & NETIF_F_RXCSUM) 904 iow(db, DM9000_RCSR, 905 (dev->features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0); 906 907 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ 908 iow(db, DM9000_GPR, 0); 909 910 /* If we are dealing with DM9000B, some extra steps are required: a 911 * manual phy reset, and setting init params. 912 */ 913 if (db->type == TYPE_DM9000B) { 914 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); 915 dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM); 916 } 917 918 ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0; 919 920 /* if wol is needed, then always set NCR_WAKEEN otherwise we end 921 * up dumping the wake events if we disable this. There is already 922 * a wake-mask in DM9000_WCR */ 923 if (db->wake_supported) 924 ncr |= NCR_WAKEEN; 925 926 iow(db, DM9000_NCR, ncr); 927 928 /* Program operating register */ 929 iow(db, DM9000_TCR, 0); /* TX Polling clear */ 930 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ 931 iow(db, DM9000_FCR, 0xff); /* Flow Control */ 932 iow(db, DM9000_SMCR, 0); /* Special Mode */ 933 /* clear TX status */ 934 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); 935 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ 936 937 /* Set address filter table */ 938 dm9000_hash_table_unlocked(dev); 939 940 imr = IMR_PAR | IMR_PTM | IMR_PRM; 941 if (db->type != TYPE_DM9000E) 942 imr |= IMR_LNKCHNG; 943 944 db->imr_all = imr; 945 946 /* Init Driver variable */ 947 db->tx_pkt_cnt = 0; 948 db->queue_pkt_len = 0; 949 dev->trans_start = jiffies; 950 } 951 952 /* Our watchdog timed out. Called by the networking layer */ 953 static void dm9000_timeout(struct net_device *dev) 954 { 955 struct board_info *db = netdev_priv(dev); 956 u8 reg_save; 957 unsigned long flags; 958 959 /* Save previous register address */ 960 spin_lock_irqsave(&db->lock, flags); 961 db->in_timeout = 1; 962 reg_save = readb(db->io_addr); 963 964 netif_stop_queue(dev); 965 dm9000_init_dm9000(dev); 966 dm9000_unmask_interrupts(db); 967 /* We can accept TX packets again */ 968 dev->trans_start = jiffies; /* prevent tx timeout */ 969 netif_wake_queue(dev); 970 971 /* Restore previous register address */ 972 writeb(reg_save, db->io_addr); 973 db->in_timeout = 0; 974 spin_unlock_irqrestore(&db->lock, flags); 975 } 976 977 static void dm9000_send_packet(struct net_device *dev, 978 int ip_summed, 979 u16 pkt_len) 980 { 981 struct board_info *dm = to_dm9000_board(dev); 982 983 /* The DM9000 is not smart enough to leave fragmented packets alone. */ 984 if (dm->ip_summed != ip_summed) { 985 if (ip_summed == CHECKSUM_NONE) 986 iow(dm, DM9000_TCCR, 0); 987 else 988 iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP); 989 dm->ip_summed = ip_summed; 990 } 991 992 /* Set TX length to DM9000 */ 993 iow(dm, DM9000_TXPLL, pkt_len); 994 iow(dm, DM9000_TXPLH, pkt_len >> 8); 995 996 /* Issue TX polling command */ 997 iow(dm, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ 998 } 999 1000 /* 1001 * Hardware start transmission. 1002 * Send a packet to media from the upper layer. 1003 */ 1004 static int 1005 dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) 1006 { 1007 unsigned long flags; 1008 struct board_info *db = netdev_priv(dev); 1009 1010 dm9000_dbg(db, 3, "%s: ", __func__); 1011 1012 if (db->tx_pkt_cnt > 1) 1013 return NETDEV_TX_BUSY; 1014 1015 spin_lock_irqsave(&db->lock, flags); 1016 1017 /* Move data to DM9000 TX RAM */ 1018 writeb(DM9000_MWCMD, db->io_addr); 1019 1020 (db->outblk)(db->io_data, skb->data, skb->len); 1021 dev->stats.tx_bytes += skb->len; 1022 1023 db->tx_pkt_cnt++; 1024 /* TX control: First packet immediately send, second packet queue */ 1025 if (db->tx_pkt_cnt == 1) { 1026 dm9000_send_packet(dev, skb->ip_summed, skb->len); 1027 } else { 1028 /* Second packet */ 1029 db->queue_pkt_len = skb->len; 1030 db->queue_ip_summed = skb->ip_summed; 1031 netif_stop_queue(dev); 1032 } 1033 1034 spin_unlock_irqrestore(&db->lock, flags); 1035 1036 /* free this SKB */ 1037 dev_consume_skb_any(skb); 1038 1039 return NETDEV_TX_OK; 1040 } 1041 1042 /* 1043 * DM9000 interrupt handler 1044 * receive the packet to upper layer, free the transmitted packet 1045 */ 1046 1047 static void dm9000_tx_done(struct net_device *dev, struct board_info *db) 1048 { 1049 int tx_status = ior(db, DM9000_NSR); /* Got TX status */ 1050 1051 if (tx_status & (NSR_TX2END | NSR_TX1END)) { 1052 /* One packet sent complete */ 1053 db->tx_pkt_cnt--; 1054 dev->stats.tx_packets++; 1055 1056 if (netif_msg_tx_done(db)) 1057 dev_dbg(db->dev, "tx done, NSR %02x ", tx_status); 1058 1059 /* Queue packet check & send */ 1060 if (db->tx_pkt_cnt > 0) 1061 dm9000_send_packet(dev, db->queue_ip_summed, 1062 db->queue_pkt_len); 1063 netif_wake_queue(dev); 1064 } 1065 } 1066 1067 struct dm9000_rxhdr { 1068 u8 RxPktReady; 1069 u8 RxStatus; 1070 __le16 RxLen; 1071 } __packed; 1072 1073 /* 1074 * Received a packet and pass to upper layer 1075 */ 1076 static void 1077 dm9000_rx(struct net_device *dev) 1078 { 1079 struct board_info *db = netdev_priv(dev); 1080 struct dm9000_rxhdr rxhdr; 1081 struct sk_buff *skb; 1082 u8 rxbyte, *rdptr; 1083 bool GoodPacket; 1084 int RxLen; 1085 1086 /* Check packet ready or not */ 1087 do { 1088 ior(db, DM9000_MRCMDX); /* Dummy read */ 1089 1090 /* Get most updated data */ 1091 rxbyte = readb(db->io_data); 1092 1093 /* Status check: this byte must be 0 or 1 */ 1094 if (rxbyte & DM9000_PKT_ERR) { 1095 dev_warn(db->dev, "status check fail: %d ", rxbyte); 1096 iow(db, DM9000_RCR, 0x00); /* Stop Device */ 1097 return; 1098 } 1099 1100 if (!(rxbyte & DM9000_PKT_RDY)) 1101 return; 1102 1103 /* A packet ready now & Get status/length */ 1104 GoodPacket = true; 1105 writeb(DM9000_MRCMD, db->io_addr); 1106 1107 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); 1108 1109 RxLen = le16_to_cpu(rxhdr.RxLen); 1110 1111 if (netif_msg_rx_status(db)) 1112 dev_dbg(db->dev, "RX: status %02x, length %04x ", 1113 rxhdr.RxStatus, RxLen); 1114 1115 /* Packet Status check */ 1116 if (RxLen < 0x40) { 1117 GoodPacket = false; 1118 if (netif_msg_rx_err(db)) 1119 dev_dbg(db->dev, "RX: Bad Packet (runt) "); 1120 } 1121 1122 if (RxLen > DM9000_PKT_MAX) { 1123 dev_dbg(db->dev, "RST: RX Len:%x ", RxLen); 1124 } 1125 1126 /* rxhdr.RxStatus is identical to RSR register. */ 1127 if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE | 1128 RSR_PLE | RSR_RWTO | 1129 RSR_LCS | RSR_RF)) { 1130 GoodPacket = false; 1131 if (rxhdr.RxStatus & RSR_FOE) { 1132 if (netif_msg_rx_err(db)) 1133 dev_dbg(db->dev, "fifo error "); 1134 dev->stats.rx_fifo_errors++; 1135 } 1136 if (rxhdr.RxStatus & RSR_CE) { 1137 if (netif_msg_rx_err(db)) 1138 dev_dbg(db->dev, "crc error "); 1139 dev->stats.rx_crc_errors++; 1140 } 1141 if (rxhdr.RxStatus & RSR_RF) { 1142 if (netif_msg_rx_err(db)) 1143 dev_dbg(db->dev, "length error "); 1144 dev->stats.rx_length_errors++; 1145 } 1146 } 1147 1148 /* Move data from DM9000 */ 1149 if (GoodPacket && 1150 ((skb = netdev_alloc_skb(dev, RxLen + 4)) != NULL)) { 1151 skb_reserve(skb, 2); 1152 rdptr = (u8 *) skb_put(skb, RxLen - 4); 1153 1154 /* Read received packet from RX SRAM */ 1155 1156 (db->inblk)(db->io_data, rdptr, RxLen); 1157 dev->stats.rx_bytes += RxLen; 1158 1159 /* Pass to upper layer */ 1160 skb->protocol = eth_type_trans(skb, dev); 1161 if (dev->features & NETIF_F_RXCSUM) { 1162 if ((((rxbyte & 0x1c) << 3) & rxbyte) == 0) 1163 skb->ip_summed = CHECKSUM_UNNECESSARY; 1164 else 1165 skb_checksum_none_assert(skb); 1166 } 1167 netif_rx(skb); 1168 dev->stats.rx_packets++; 1169 1170 } else { 1171 /* need to dump the packet's data */ 1172 1173 (db->dumpblk)(db->io_data, RxLen); 1174 } 1175 } while (rxbyte & DM9000_PKT_RDY); 1176 } 1177 1178 static irqreturn_t dm9000_interrupt(int irq, void *dev_id) 1179 { 1180 struct net_device *dev = dev_id; 1181 struct board_info *db = netdev_priv(dev); 1182 int int_status; 1183 unsigned long flags; 1184 u8 reg_save; 1185 1186 dm9000_dbg(db, 3, "entering %s ", __func__); 1187 1188 /* A real interrupt coming */ 1189 1190 /* holders of db->lock must always block IRQs */ 1191 spin_lock_irqsave(&db->lock, flags); 1192 1193 /* Save previous register address */ 1194 reg_save = readb(db->io_addr); 1195 1196 dm9000_mask_interrupts(db); 1197 /* Got DM9000 interrupt status */ 1198 int_status = ior(db, DM9000_ISR); /* Got ISR */ 1199 iow(db, DM9000_ISR, int_status); /* Clear ISR status */ 1200 1201 if (netif_msg_intr(db)) 1202 dev_dbg(db->dev, "interrupt status %02x ", int_status); 1203 1204 /* Received the coming packet */ 1205 if (int_status & ISR_PRS) 1206 dm9000_rx(dev); 1207 1208 /* Trnasmit Interrupt check */ 1209 if (int_status & ISR_PTS) 1210 dm9000_tx_done(dev, db); 1211 1212 if (db->type != TYPE_DM9000E) { 1213 if (int_status & ISR_LNKCHNG) { 1214 /* fire a link-change request */ 1215 schedule_delayed_work(&db->phy_poll, 1); 1216 } 1217 } 1218 1219 dm9000_unmask_interrupts(db); 1220 /* Restore previous register address */ 1221 writeb(reg_save, db->io_addr); 1222 1223 spin_unlock_irqrestore(&db->lock, flags); 1224 1225 return IRQ_HANDLED; 1226 } 1227 1228 static irqreturn_t dm9000_wol_interrupt(int irq, void *dev_id) 1229 { 1230 struct net_device *dev = dev_id; 1231 struct board_info *db = netdev_priv(dev); 1232 unsigned long flags; 1233 unsigned nsr, wcr; 1234 1235 spin_lock_irqsave(&db->lock, flags); 1236 1237 nsr = ior(db, DM9000_NSR); 1238 wcr = ior(db, DM9000_WCR); 1239 1240 dev_dbg(db->dev, "%s: NSR=0x%02x, WCR=0x%02x ", __func__, nsr, wcr); 1241 1242 if (nsr & NSR_WAKEST) { 1243 /* clear, so we can avoid */ 1244 iow(db, DM9000_NSR, NSR_WAKEST); 1245 1246 if (wcr & WCR_LINKST) 1247 dev_info(db->dev, "wake by link status change "); 1248 if (wcr & WCR_SAMPLEST) 1249 dev_info(db->dev, "wake by sample packet "); 1250 if (wcr & WCR_MAGICST) 1251 dev_info(db->dev, "wake by magic packet "); 1252 if (!(wcr & (WCR_LINKST | WCR_SAMPLEST | WCR_MAGICST))) 1253 dev_err(db->dev, "wake signalled with no reason? " 1254 "NSR=0x%02x, WSR=0x%02x ", nsr, wcr); 1255 } 1256 1257 spin_unlock_irqrestore(&db->lock, flags); 1258 1259 return (nsr & NSR_WAKEST) ? IRQ_HANDLED : IRQ_NONE; 1260 } 1261 1262 #ifdef CONFIG_NET_POLL_CONTROLLER 1263 /* 1264 *Used by netconsole 1265 */ 1266 static void dm9000_poll_controller(struct net_device *dev) 1267 { 1268 disable_irq(dev->irq); 1269 dm9000_interrupt(dev->irq, dev); 1270 enable_irq(dev->irq); 1271 } 1272 #endif 1273 1274 /* 1275 * Open the interface. 1276 * The interface is opened whenever "ifconfig" actives it. 1277 */ 1278 static int 1279 dm9000_open(struct net_device *dev) 1280 { 1281 struct board_info *db = netdev_priv(dev); 1282 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; 1283 1284 if (netif_msg_ifup(db)) 1285 dev_dbg(db->dev, "enabling %s ", dev->name); 1286 1287 /* If there is no IRQ type specified, default to something that 1288 * may work, and tell the user that this is a problem */ 1289 1290 if (irqflags == IRQF_TRIGGER_NONE) 1291 irqflags = irq_get_trigger_type(dev->irq); 1292 1293 if (irqflags == IRQF_TRIGGER_NONE) 1294 dev_warn(db->dev, "WARNING: no IRQ resource flags set. "); 1295 1296 irqflags |= IRQF_SHARED; 1297 1298 /* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */ 1299 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ 1300 mdelay(1); /* delay needs by DM9000B */ 1301 1302 /* Initialize DM9000 board */ 1303 dm9000_init_dm9000(dev); 1304 1305 if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev)) 1306 return -EAGAIN; 1307 /* Now that we have an interrupt handler hooked up we can unmask 1308 * our interrupts 1309 */ 1310 dm9000_unmask_interrupts(db); 1311 1312 /* Init driver variable */ 1313 db->dbug_cnt = 0; 1314 1315 mii_check_media(&db->mii, netif_msg_link(db), 1); 1316 netif_start_queue(dev); 1317 1318 /* Poll initial link status */ 1319 schedule_delayed_work(&db->phy_poll, 1); 1320 1321 return 0; 1322 } 1323 1324 static void 1325 dm9000_shutdown(struct net_device *dev) 1326 { 1327 struct board_info *db = netdev_priv(dev); 1328 1329 /* RESET device */ 1330 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ 1331 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ 1332 dm9000_mask_interrupts(db); 1333 iow(db, DM9000_RCR, 0x00); /* Disable RX */ 1334 } 1335 1336 /* 1337 * Stop the interface. 1338 * The interface is stopped when it is brought. 1339 */ 1340 static int 1341 dm9000_stop(struct net_device *ndev) 1342 { 1343 struct board_info *db = netdev_priv(ndev); 1344 1345 if (netif_msg_ifdown(db)) 1346 dev_dbg(db->dev, "shutting down %s ", ndev->name); 1347 1348 cancel_delayed_work_sync(&db->phy_poll); 1349 1350 netif_stop_queue(ndev); 1351 netif_carrier_off(ndev); 1352 1353 /* free interrupt */ 1354 free_irq(ndev->irq, ndev); 1355 1356 dm9000_shutdown(ndev); 1357 1358 return 0; 1359 } 1360 1361 static const struct net_device_ops dm9000_netdev_ops = { 1362 .ndo_open = dm9000_open, 1363 .ndo_stop = dm9000_stop, 1364 .ndo_start_xmit = dm9000_start_xmit, 1365 .ndo_tx_timeout = dm9000_timeout, 1366 .ndo_set_rx_mode = dm9000_hash_table, 1367 .ndo_do_ioctl = dm9000_ioctl, 1368 .ndo_change_mtu = eth_change_mtu, 1369 .ndo_set_features = dm9000_set_features, 1370 .ndo_validate_addr = eth_validate_addr, 1371 .ndo_set_mac_address = eth_mac_addr, 1372 #ifdef CONFIG_NET_POLL_CONTROLLER 1373 .ndo_poll_controller = dm9000_poll_controller, 1374 #endif 1375 }; 1376 1377 static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev) 1378 { 1379 struct dm9000_plat_data *pdata; 1380 struct device_node *np = dev->of_node; 1381 const void *mac_addr; 1382 1383 if (!IS_ENABLED(CONFIG_OF) || !np) 1384 return ERR_PTR(-ENXIO); 1385 1386 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1387 if (!pdata) 1388 return ERR_PTR(-ENOMEM); 1389 1390 if (of_find_property(np, "davicom,ext-phy", NULL)) 1391 pdata->flags |= DM9000_PLATF_EXT_PHY; 1392 if (of_find_property(np, "davicom,no-eeprom", NULL)) 1393 pdata->flags |= DM9000_PLATF_NO_EEPROM; 1394 1395 mac_addr = of_get_mac_address(np); 1396 if (mac_addr) 1397 memcpy(pdata->dev_addr, mac_addr, sizeof(pdata->dev_addr)); 1398 1399 return pdata; 1400 } 1401 1402 /* 1403 * Search DM9000 board, allocate space and register it 1404 */ 1405 static int 1406 dm9000_probe(struct platform_device *pdev) 1407 { 1408 struct dm9000_plat_data *pdata = dev_get_platdata(&pdev->dev); 1409 struct board_info *db; /* Point a board information structure */ 1410 struct net_device *ndev; 1411 struct device *dev = &pdev->dev; 1412 const unsigned char *mac_src; 1413 int ret = 0; 1414 int iosize; 1415 int i; 1416 u32 id_val; 1417 int reset_gpios; 1418 enum of_gpio_flags flags; 1419 struct regulator *power; 1420 1421 power = devm_regulator_get(dev, "vcc"); 1422 if (IS_ERR(power)) { 1423 if (PTR_ERR(power) == -EPROBE_DEFER) 1424 return -EPROBE_DEFER; 1425 dev_dbg(dev, "no regulator provided "); 1426 } else { 1427 ret = regulator_enable(power); 1428 if (ret != 0) { 1429 dev_err(dev, 1430 "Failed to enable power regulator: %d ", ret); 1431 return ret; 1432 } 1433 dev_dbg(dev, "regulator enabled "); 1434 } 1435 1436 reset_gpios = of_get_named_gpio_flags(dev->of_node, "reset-gpios", 0, 1437 &flags); 1438 if (gpio_is_valid(reset_gpios)) { 1439 ret = devm_gpio_request_one(dev, reset_gpios, flags, 1440 "dm9000_reset"); 1441 if (ret) { 1442 dev_err(dev, "failed to request reset gpio %d: %d ", 1443 reset_gpios, ret); 1444 return -ENODEV; 1445 } 1446 1447 /* According to manual PWRST# Low Period Min 1ms */ 1448 msleep(2); 1449 gpio_set_value(reset_gpios, 1); 1450 /* Needs 3ms to read eeprom when PWRST is deasserted */ 1451 msleep(4); 1452 } 1453 1454 if (!pdata) { 1455 pdata = dm9000_parse_dt(&pdev->dev); 1456 if (IS_ERR(pdata)) 1457 return PTR_ERR(pdata); 1458 } 1459 1460 /* Init network device */ 1461 ndev = alloc_etherdev(sizeof(struct board_info)); 1462 if (!ndev) 1463 return -ENOMEM; 1464 1465 SET_NETDEV_DEV(ndev, &pdev->dev); 1466 1467 dev_dbg(&pdev->dev, "dm9000_probe() "); 1468 1469 /* setup board info structure */ 1470 db = netdev_priv(ndev); 1471 1472 db->dev = &pdev->dev; 1473 db->ndev = ndev; 1474 1475 spin_lock_init(&db->lock); 1476 mutex_init(&db->addr_lock); 1477 1478 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); 1479 1480 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1481 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1482 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1483 1484 if (db->addr_res == NULL || db->data_res == NULL || 1485 db->irq_res == NULL) { 1486 dev_err(db->dev, "insufficient resources "); 1487 ret = -ENOENT; 1488 goto out; 1489 } 1490 1491 db->irq_wake = platform_get_irq(pdev, 1); 1492 if (db->irq_wake >= 0) { 1493 dev_dbg(db->dev, "wakeup irq %d ", db->irq_wake); 1494 1495 ret = request_irq(db->irq_wake, dm9000_wol_interrupt, 1496 IRQF_SHARED, dev_name(db->dev), ndev); 1497 if (ret) { 1498 dev_err(db->dev, "cannot get wakeup irq (%d) ", ret); 1499 } else { 1500 1501 /* test to see if irq is really wakeup capable */ 1502 ret = irq_set_irq_wake(db->irq_wake, 1); 1503 if (ret) { 1504 dev_err(db->dev, "irq %d cannot set wakeup (%d) ", 1505 db->irq_wake, ret); 1506 ret = 0; 1507 } else { 1508 irq_set_irq_wake(db->irq_wake, 0); 1509 db->wake_supported = 1; 1510 } 1511 } 1512 } 1513 1514 iosize = resource_size(db->addr_res); 1515 db->addr_req = request_mem_region(db->addr_res->start, iosize, 1516 pdev->name); 1517 1518 if (db->addr_req == NULL) { 1519 dev_err(db->dev, "cannot claim address reg area "); 1520 ret = -EIO; 1521 goto out; 1522 } 1523 1524 db->io_addr = ioremap(db->addr_res->start, iosize); 1525 1526 if (db->io_addr == NULL) { 1527 dev_err(db->dev, "failed to ioremap address reg "); 1528 ret = -EINVAL; 1529 goto out; 1530 } 1531 1532 iosize = resource_size(db->data_res); 1533 db->data_req = request_mem_region(db->data_res->start, iosize, 1534 pdev->name); 1535 1536 if (db->data_req == NULL) { 1537 dev_err(db->dev, "cannot claim data reg area "); 1538 ret = -EIO; 1539 goto out; 1540 } 1541 1542 db->io_data = ioremap(db->data_res->start, iosize); 1543 1544 if (db->io_data == NULL) { 1545 dev_err(db->dev, "failed to ioremap data reg "); 1546 ret = -EINVAL; 1547 goto out; 1548 } 1549 1550 /* fill in parameters for net-dev structure */ 1551 ndev->base_addr = (unsigned long)db->io_addr; 1552 ndev->irq = db->irq_res->start; 1553 1554 /* ensure at least we have a default set of IO routines */ 1555 dm9000_set_io(db, iosize); 1556 1557 /* check to see if anything is being over-ridden */ 1558 if (pdata != NULL) { 1559 /* check to see if the driver wants to over-ride the 1560 * default IO width */ 1561 1562 if (pdata->flags & DM9000_PLATF_8BITONLY) 1563 dm9000_set_io(db, 1); 1564 1565 if (pdata->flags & DM9000_PLATF_16BITONLY) 1566 dm9000_set_io(db, 2); 1567 1568 if (pdata->flags & DM9000_PLATF_32BITONLY) 1569 dm9000_set_io(db, 4); 1570 1571 /* check to see if there are any IO routine 1572 * over-rides */ 1573 1574 if (pdata->inblk != NULL) 1575 db->inblk = pdata->inblk; 1576 1577 if (pdata->outblk != NULL) 1578 db->outblk = pdata->outblk; 1579 1580 if (pdata->dumpblk != NULL) 1581 db->dumpblk = pdata->dumpblk; 1582 1583 db->flags = pdata->flags; 1584 } 1585 1586 #ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL 1587 db->flags |= DM9000_PLATF_SIMPLE_PHY; 1588 #endif 1589 1590 dm9000_reset(db); 1591 1592 /* try multiple times, DM9000 sometimes gets the read wrong */ 1593 for (i = 0; i < 8; i++) { 1594 id_val = ior(db, DM9000_VIDL); 1595 id_val |= (u32)ior(db, DM9000_VIDH) << 8; 1596 id_val |= (u32)ior(db, DM9000_PIDL) << 16; 1597 id_val |= (u32)ior(db, DM9000_PIDH) << 24; 1598 1599 if (id_val == DM9000_ID) 1600 break; 1601 dev_err(db->dev, "read wrong id 0x%08x ", id_val); 1602 } 1603 1604 if (id_val != DM9000_ID) { 1605 dev_err(db->dev, "wrong id: 0x%08x ", id_val); 1606 ret = -ENODEV; 1607 goto out; 1608 } 1609 1610 /* Identify what type of DM9000 we are working on */ 1611 1612 id_val = ior(db, DM9000_CHIPR); 1613 dev_dbg(db->dev, "dm9000 revision 0x%02x ", id_val); 1614 1615 switch (id_val) { 1616 case CHIPR_DM9000A: 1617 db->type = TYPE_DM9000A; 1618 break; 1619 case CHIPR_DM9000B: 1620 db->type = TYPE_DM9000B; 1621 break; 1622 default: 1623 dev_dbg(db->dev, "ID %02x => defaulting to DM9000E ", id_val); 1624 db->type = TYPE_DM9000E; 1625 } 1626 1627 /* dm9000a/b are capable of hardware checksum offload */ 1628 if (db->type == TYPE_DM9000A || db->type == TYPE_DM9000B) { 1629 ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM; 1630 ndev->features |= ndev->hw_features; 1631 } 1632 1633 /* from this point we assume that we have found a DM9000 */ 1634 1635 ndev->netdev_ops = &dm9000_netdev_ops; 1636 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 1637 ndev->ethtool_ops = &dm9000_ethtool_ops; 1638 1639 db->msg_enable = NETIF_MSG_LINK; 1640 db->mii.phy_id_mask = 0x1f; 1641 db->mii.reg_num_mask = 0x1f; 1642 db->mii.force_media = 0; 1643 db->mii.full_duplex = 0; 1644 db->mii.dev = ndev; 1645 db->mii.mdio_read = dm9000_phy_read; 1646 db->mii.mdio_write = dm9000_phy_write; 1647 1648 mac_src = "eeprom"; 1649 1650 /* try reading the node address from the attached EEPROM */ 1651 for (i = 0; i < 6; i += 2) 1652 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); 1653 1654 if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) { 1655 mac_src = "platform data"; 1656 memcpy(ndev->dev_addr, pdata->dev_addr, ETH_ALEN); 1657 } 1658 1659 if (!is_valid_ether_addr(ndev->dev_addr)) { 1660 /* try reading from mac */ 1661 1662 mac_src = "chip"; 1663 for (i = 0; i < 6; i++) 1664 ndev->dev_addr[i] = ior(db, i+DM9000_PAR); 1665 } 1666 1667 if (!is_valid_ether_addr(ndev->dev_addr)) { 1668 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " 1669 "set using ifconfig ", ndev->name); 1670 1671 eth_hw_addr_random(ndev); 1672 mac_src = "random"; 1673 } 1674 1675 1676 platform_set_drvdata(pdev, ndev); 1677 ret = register_netdev(ndev); 1678 1679 if (ret == 0) 1680 printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s) ", 1681 ndev->name, dm9000_type_to_char(db->type), 1682 db->io_addr, db->io_data, ndev->irq, 1683 ndev->dev_addr, mac_src); 1684 return 0; 1685 1686 out: 1687 dev_err(db->dev, "not found (%d). ", ret); 1688 1689 dm9000_release_board(pdev, db); 1690 free_netdev(ndev); 1691 1692 return ret; 1693 } 1694 1695 static int 1696 dm9000_drv_suspend(struct device *dev) 1697 { 1698 struct platform_device *pdev = to_platform_device(dev); 1699 struct net_device *ndev = platform_get_drvdata(pdev); 1700 struct board_info *db; 1701 1702 if (ndev) { 1703 db = netdev_priv(ndev); 1704 db->in_suspend = 1; 1705 1706 if (!netif_running(ndev)) 1707 return 0; 1708 1709 netif_device_detach(ndev); 1710 1711 /* only shutdown if not using WoL */ 1712 if (!db->wake_state) 1713 dm9000_shutdown(ndev); 1714 } 1715 return 0; 1716 } 1717 1718 static int 1719 dm9000_drv_resume(struct device *dev) 1720 { 1721 struct platform_device *pdev = to_platform_device(dev); 1722 struct net_device *ndev = platform_get_drvdata(pdev); 1723 struct board_info *db = netdev_priv(ndev); 1724 1725 if (ndev) { 1726 if (netif_running(ndev)) { 1727 /* reset if we were not in wake mode to ensure if 1728 * the device was powered off it is in a known state */ 1729 if (!db->wake_state) { 1730 dm9000_init_dm9000(ndev); 1731 dm9000_unmask_interrupts(db); 1732 } 1733 1734 netif_device_attach(ndev); 1735 } 1736 1737 db->in_suspend = 0; 1738 } 1739 return 0; 1740 } 1741 1742 static const struct dev_pm_ops dm9000_drv_pm_ops = { 1743 .suspend = dm9000_drv_suspend, 1744 .resume = dm9000_drv_resume, 1745 }; 1746 1747 static int 1748 dm9000_drv_remove(struct platform_device *pdev) 1749 { 1750 struct net_device *ndev = platform_get_drvdata(pdev); 1751 1752 unregister_netdev(ndev); 1753 dm9000_release_board(pdev, netdev_priv(ndev)); 1754 free_netdev(ndev); /* free device structure */ 1755 1756 dev_dbg(&pdev->dev, "released and freed device "); 1757 return 0; 1758 } 1759 1760 #ifdef CONFIG_OF 1761 static const struct of_device_id dm9000_of_matches[] = { 1762 { .compatible = "davicom,dm9000", }, 1763 { /* sentinel */ } 1764 }; 1765 MODULE_DEVICE_TABLE(of, dm9000_of_matches); 1766 #endif 1767 1768 static struct platform_driver dm9000_driver = { 1769 .driver = { 1770 .name = "dm9000", 1771 .pm = &dm9000_drv_pm_ops, 1772 .of_match_table = of_match_ptr(dm9000_of_matches), 1773 }, 1774 .probe = dm9000_probe, 1775 .remove = dm9000_drv_remove, 1776 }; 1777 1778 module_platform_driver(dm9000_driver); 1779 1780 MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); 1781 MODULE_DESCRIPTION("Davicom DM9000 network driver"); 1782 MODULE_LICENSE("GPL"); 1783 MODULE_ALIAS("platform:dm9000");
DM9000 驱动的实现与具体的CPU无关，在将该驱动移植到特定的平台时，只需要在板文件中为与板上 DM9000 对应的平台设备的寄存器和数据基地址进行赋值，并指定正确的 IRQ 资源即可，以下代码给出了在 arch/arm/mach-at91/board-sam9261ek.c 板文件中对DM9000 添加的内容：
1 /** 2 * board-sam9261ek 板文件中的 DM9000 的平台设备 3 */ 4 5 static struct resource dm9000_resource[] = { 6 [0] = { 7 .start = AT91_CHIPSELECT_2, 8 .end = AT91_CHIPSELECT_2 + 3, 9 .flags = IORESOURCE_MEM 10 }, 11 [1] = { 12 .start = AT91_CHIPSELECT_2 + 0x44, 13 .end = AT91_CHIPSELECT_2 + 0xFF, 14 .flags = IORESOURCE_MEM 15 }, 16 [2] = { 17 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE 18 | IORESOURCE_IRQ_HIGHEDGE, 19 } 20 }; 21 22 static struct dm9000_plat_data dm9000_platdata = { 23 .flags = DM9000_PLATF_16BITONLY |DM9000_PLATF_NO_EEPROM, 24 }; 25 26 static struct platform_device dm9000_device = { 27 .name = "dm9000", 28 .id = 0, 29 .num_resource = ARRAY_SIZE(dm9000_resource), 30 .resource = dm9000_resource, 31 .dev = { 32 .platform_data = &dm9000_platdata, 33 } 34 };
对 Linux 网络设备驱动体系结构的层次化设计实现了对上层协议接口的统一 和 硬件驱动对下层多样化硬件设备的可适应。我们需要完成的工作集中在设备驱动功能层，网络设备接口层 net_device 结构体的存在将千变万化的网络设备进行抽象，使得设备功能层中除数据包接收以外的主体工作都由填充 net_device 的属性和函数指针完成。
在分析 net_device 数据结构的基础上，给出了设备驱动功能层设备初始化、数据包收发、打开和释放等函数的设计模板，这些模板对实际设备驱动的开发具有直接指导意义。有了这些模板，我们在设计具体设备的驱动时，不再需要关心程序的体系，而可以将精力集中于硬件操作本身。
在 Linux 网络子系统和设备驱动中，套接字缓冲区 sk_buff 发挥着巨大的作用，它是所有数据流动的载体。网络设备驱动和上层协议之间也基于此结构进行数据包交互。