Title:1024-Point Pipeline FFT Processor with Pointer FIFOs based on FPGA
Abstract:Design and optimized implemention of a 16-bit and 32-bit 1024 points pipeline FFT processor is presented in this paper.The architecture of the FFT is based on R22SDF algorithm with new pointer FIFO embeded with grey code counters.It is implemented in Spartan-3E,Spartan-6 and Virtex-4 devices and fully tested by method of simulation using SMIMS VeriLink as a bridge that connets software and real hardware - FPGA- targets.The implementation results show that our pointer FIFO FFT processor could use lower resource, but achieve higher performance.Our 16-bit 1024-point FFT processor only costs 2580 slices,2030 slice flip flops and just 2 block RAMs,achieving the maxium clock frequency.