1 -- Dual port RAM with enable on each port 2 -- Xilinx rams_14 3 4 library ieee; 5 use ieee.std_logic_1164.all; 6 use ieee.std_logic_unsigned.all; 7 8 entity dp_ram is 9 port(clk : in std_logic; 10 ena : in std_logic; 11 enb : in std_logic; 12 wea : in std_logic; 13 addra : in std_logic_vector(10 downto 0); 14 addrb : in std_logic_vector(10 downto 0); 15 dia : in std_logic_vector(7 downto 0); 16 doa : out std_logic_vector(7 downto 0); 17 dob : out std_logic_vector(7 downto 0) 18 ); 19 end dp_ram; 20 21 architecture rtl of dp_ram is 22 type ram_type is array(2047 downto 0) of std_logic_vector(7 downto 0); 23 signal RAM : ram_type; 24 signal read_addra : std_logic_vector(10 downto 0); 25 signal read_addrb : std_logic_vector(10 downto 0); 26 begin 27 28 process(clk) 29 begin 30 if rising_edge(clk) then 31 if ena = '1' then 32 if wea = '1' then 33 RAM(conv_integer(addra)) <= dia; 34 end if; 35 read_addra <= addra; 36 end if; 37 if enb = '1' then 38 read_addrb <= addrb; 39 end if; 40 end if; 41 end process; 42 43 doa <= RAM(conv_integer(read_addra)); 44 dob <= RAM(conv_integer(read_addrb)); 45 46 end rtl;