How can I discribe a ROM in VHDL

 1 library ieee;
 2 use ieee.std_logic_1164.all;
 3 use ieee.numeric_std.all;
 4 
 5 entity single_port_rom is
 6 
 7   port
 8   (
 9     addr : in natural range 0 to 255;
10     clk  : in std_logic;
11     q    : out std_logic_vector(7 downto 0)
12   );
13 
14 end entity;
15 
16 architecture rtl of single_port_rom is
17 
18   -- Build a 2-D array type for the RoM
19   subtype word_t is std_logic_vector(7 downto 0);
20   type memory_t is array(255 downto 0) of word_t;
21 
22   function init_rom
23     return memory_t is
24     variable tmp : memory_t := (others => (others => '0'));
25   begin
26     for addr_pos in 0 to 255 loop
27         -- Initialize each address with the address itself
28       tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, 8));
29     end loop;
30     return tmp;
31   end init_rom;
32 
33   -- Declare the ROM signal and specify a default value.  Quartus II
34   -- will create a memory initialization file (.mif) based on the 
35   -- default value.
36   signal rom : memory_t := init_rom;
37 
38 begin

 1 library ieee;
 2 use ieee.std_logic_1164.all;
 3 
 4 entity ROM is
 5   port ( address : in std_logic_vector(3 downto 0);
 6          data : out std_logic_vector(7 downto 0) );
 7 end entity ROM;
 8 
 9 architecture behavioral of ROM is
10   type mem is array ( 0 to 2**4 - 1) of std_logic_vector(7 downto 0);
11   constant my_Rom : mem := (
12     0  => "00000000",
13     1  => "00000001",
14     2  => "00000010",
15     3  => "00000011",
16     4  => "00000100",
17     5  => "11110000",
18     6  => "11110000",
19     7  => "11110000",
20     8  => "11110000",
21     9  => "11110000",
22     10 => "11110000",
23     11 => "11110000",
24     12 => "11110000",
25     13 => "11110000",
26     14 => "11110000",
27     15 => "11110000");
28 begin
29    process (address)
30    begin
31      case address is
32        when "0000" => data <= my_rom(0);
33        when "0001" => data <= my_rom(1);
34        when "0010" => data <= my_rom(2);
35        when "0011" => data <= my_rom(3);
36        when "0100" => data <= my_rom(4);
37        when "0101" => data <= my_rom(5);
38        when "0110" => data <= my_rom(6);
39        when "0111" => data <= my_rom(7);
40        when "1000" => data <= my_rom(8);
41        when "1001" => data <= my_rom(9);
42        when "1010" => data <= my_rom(10);

 1 library ieee;
 2 use ieee.std_logic_1164.all;
 3 use ieee.numeric_std.all;
 4 
 5 entity single_port_rom is
 6 
 7   generic
 8   (
 9     DATA_WIDTH : natural := 8;
10     ADDR_WIDTH : natural := 8
11   );
12 
13   port
14   (
15     clk  : in std_logic;
16     addr : in natural range 0 to 2**ADDR_WIDTH - 1;
17     q    : out std_logic_vector((DATA_WIDTH -1) downto 0)
18   );
19 
20 end entity;
21 
22 architecture rtl of single_port_rom is
23 
24   -- Build a 2-D array type for the RoM
25   subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
26   type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
27 
28   function init_rom
29     return memory_t is 
30     variable tmp : memory_t := (others => (others => '0'));
31   begin
32     for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop
33       -- Initialize each address with the address itself
34       tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH));
35     end loop;
36     return tmp;
37   end init_rom;
38 
39   -- Declare the ROM signal and specify a default value.  Quartus II
40   -- will create a memory initialization file (.mif) based on the 
41   -- default value.
42   signal rom : memory_t := init_rom;
43 
44 begin
45 
46   process(clk)
47   begin
48     if(rising_edge(clk)) then
49       q <= rom(addr);
50     end if;
51   end process;
52 
53 end rtl;

 1 --------------------------------------------------------------
 2 -- 32*8 ROM module (ESD Book Chapter 5)
 3 -- by Weijun Zhang, 04/2001
 4 --
 5 -- ROM model has predefined content for read only purpose
 6 --------------------------------------------------------------
 7 
 8 library ieee;
 9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_arith.all;
11 use ieee.std_logic_unsigned.all;
12 
13 entity ROM is
14   port( Clock : in std_logic;
15     Reset    : in std_logic;
16     Enable   : in std_logic;
17     Read     : in std_logic;
18     Address  : in std_logic_vector(4 downto 0);
19     Data_out : out std_logic_vector(7 downto 0)
20   );
21 end ROM;
22 
23 --------------------------------------------------------------
24 
25 architecture Behav of ROM is
26 
27   type ROM_Array is array (0 to 31)
28 of std_logic_vector(7 downto 0);
29 
30   constant Content : ROM_Array := (
31     0      => "00000001",   -- Suppose ROM has
32     1      => "00000010",   -- prestored value
33     2      => "00000011",   -- like this table
34     3      => "00000100", --
35     4      => "00000101",   --
36     5      => "00000110", --
37     6      => "00000111",   --
38     7      => "00001000", --
39     8      => "00001001", --
40     9      => "00001010", --
41     10     => "00001011",  --
42     11     => "00001100", --
43     12     => "00001101", --
44     13     => "00001110",  --
45     14     => "00001111",  --
46     others => "11111111"   --
47   );
48 
49 begin
50   process(Clock, Reset, Read, Address)
51   begin
52     if( Reset = '1' ) then
53       Data_out <= "ZZZZZZZZ";
54     elsif( Clock'event and Clock = '1' ) then
55       if Enable = '1' then
56         if( Read = '1' ) then
57           Data_out <= Content(conv_integer(Address));
58         else
59           Data_out <= "ZZZZZZZZ";
60         end if;
61       end if;
62     end if;
63   end process;
64 end Behav;

43        when "1011" => data <= my_rom(11);
44        when "1100" => data <= my_rom(12);
45        when "1101" => data <= my_rom(13);
46        when "1110" => data <= my_rom(14);
47        when "1111" => data <= my_rom(15);
48        when others => data <= "00000000";
49      end case;
50   end process;
51 end architecture behavioral;

39 
40   process(clk)
41   begin
42     if(rising_edge(clk)) then
43       q <= rom(addr);
44     end if;
45   end process;
46 
47 end rtl;