/* * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <config.h> #include <asm/arch/mx6.h> #ifdef CONFIG_FLASH_HEADER #ifndef CONFIG_FLASH_HEADER_OFFSET # error "Must define the offset of flash header" #endif #define CPU_2_BE_32(l) ((((l) & 0x000000FF) << 24) | (((l) & 0x0000FF00) << 8) | (((l) & 0x00FF0000) >> 8) | (((l) & 0xFF000000) >> 24)) #define MXC_DCD_ITEM(i, addr, val) dcd_node_##i: .word CPU_2_BE_32(addr) ; .word CPU_2_BE_32(val) ; .section ".text.flasheader", "x" b _start .org CONFIG_FLASH_HEADER_OFFSET ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */ app_code_jump_v: .word _start reserv1: .word 0x0 dcd_ptr: .word dcd_hdr boot_data_ptr: .word boot_data self_ptr: .word ivt_header app_code_csf: .word 0x0 reserv2: .word 0x0 boot_data: .word TEXT_BASE image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET plugin: .word 0x0 dcd_hdr: .word 0xD202A040 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0xCC029C04 /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */ dcd_hdr: .word 0x40A002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x049C02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */ /* DCD */ /* DDR3 initialization based on the MX6Q Auto Reference Design (ARD) */ /* DDR IO TYPE: */ # IOMUXC_BASE_ADDR = 0x20e00000 # DDR IO TYPE MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000) MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000) /* CLOCK: */ MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030) MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030) /* ADDRESS: */ MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030) MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030) MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030) /* CONTROL: */ MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030) MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x58c, 0x00000000) /* configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */ MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x59c, 0x00000030) MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5a0, 0x00000030) MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x78c, 0x00000030) /* DATA STROBE: */ MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000) MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x5a8, 0x00000018) MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5b0, 0x00000018) MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x524, 0x00000018) MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x51c, 0x00000018) MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x518, 0x00000018) MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x50c, 0x00000018) MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5b8, 0x00000018) MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x5c0, 0x00000018) /* DATA: */ MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x774, 0x00020000) MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x784, 0x00000018) MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x788, 0x00000018) MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x794, 0x00000018) MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x79c, 0x00000018) MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x7a0, 0x00000018) MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x7a4, 0x00000018) MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a8, 0x00000018) MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000018) MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x5ac, 0x00000018) MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x5b4, 0x00000018) MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x528, 0x00000018) MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x520, 0x00000018) MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x514, 0x00000018) MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x510, 0x00000018) MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x5bc, 0x00000018) MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x5c4, 0x00000018) # MMDC_P0_BASE_ADDR = 0x021b0000 # MMDC_P1_BASE_ADDR = 0x021b4000 MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003) MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F) MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F) MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F) MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F) /* Read DQS Gating calibration */ MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x4333033F) MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x032C031D) MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83c, 0x43200332) MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x031A026A) /* Read calibration */ MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4D464746) MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x47453F4D) /* Write calibration */ MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3E434440) MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x47384839) /* read data bit delay: (3 is the reccommended default value, although out of reset value is 0): */ MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333) MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x824, 0x33333333) MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x828, 0x33333333) MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333) MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x820, 0x33333333) MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x824, 0x33333333) MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x828, 0x33333333) /* Complete calibration by forced measurement: */ MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800) /* MMDC init: */ MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x004, 0x00020036) MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x008, 0x09444040) MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7955) MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x010, 0xFF328F64) MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x018, 0x00001740) MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) /* t during MMDC set up */ MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2) /* t values */ MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x008F1023) MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000047) MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000) /* Mode register writes */ MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032) MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033) MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031) MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030) MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x00025576) MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) #endif