IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language
The assign procedural continuous assignment statement shall override all procedural assignments to a variable. The deassign procedural statement shall end a procedural continuous assignment to a variable. The value of the variable shall remain the same until the reg is assigned a new value through a procedural assignment or a procedural continuous assignment. The assign and deassign procedural statements allow, for example, modeling of asynchronous clear/preset on a D-type edge-triggered flip-flop, where the clock is inhibited when the clear or preset is active.
If the keyword assign is applied to a variable for which there is already a procedural continuous assignment, then this new procedural continuous assignment shall deassign the variable before making the new procedural continuous assignment.
Example:
The following example shows a use of the assign and deassign procedural statements in a behavioral description of a D-type flip-flop with preset and clear inputs.
module dff (q, d, clear, preset, clock); output q; input d, clear, preset, clock; reg q; always @(clear or preset) if (!clear) assign q = 0; else if (!preset) assign q = 1; else deassign q; always @(posedge clock) q = d; endmodule
If either clear or preset is low, then the output q will be held continuously to the appropriate constant value and a positive edge on the clock will not affect q.When both the clear and preset are high, then q is deassigned.