1、如图是带有使能端和复位端的时钟同步8位寄存器组的逻辑和模块接口图
2、verilog程序
module register8(ena,clk,data,rst,out);
input ena,clk,rst;
input[7:0] data;
output[7:0] out;
reg[7:0] out;
always@(posedge clk)
begin
if(!rst)
out<=0;
else if(ena)
out<=data;
else ;
end
endmodule
made by qidaiYMM, yout comment is appreciated.
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