verdi启动

两个文件。Makefile,dump_fsdb_vcs.tcl

Makefile:

#veridi simulation makefile for 
export f=filelist.f
#all
all: clean com_vcs run_vcs
#start compile
com_vcs:
vcs
-sverilog
-debug_pp
-LDFLAGS
-rdynamic
-full64
+v2k
-l com.log
-P ${LD_LIBRARY_PATH}/novas.tab ${LD_LIBRARY_PATH}/pli.a
-f $(f)

#start simulate
run_vcs:
./simv -ucli -i dump_fsdb_vcs.tcl +fsdb +autoflush -l sim.log

#debug
debug:
verdi
-sv
-f $(f)
-sverilog
-ssf tb.fsdb
-nologo

#clean file
clean:
@rm -rf csrc DVEfiles simv simv.daidir ucli.key VCS*
@rm -rf *.log *.fsdb novas.* verdiLog *.vpd *.ddc *.svf *.SDF *Synth *Netlist* work vsim* transcript

注意：LD_BERARY_PATH

dump_fsdb_vcs.tcl:

global env
fsdbDumpfile "tb.fsdb"
fsdbDumpvars 0 "tb_top"
run

操作：

在terminal输入make all f=filelist.f

make debug

即可进入verdi界面。加载.fsdb文件查看仿真波形