数字系统设计练习（五）—— 选择语句的使用

一、实验硬软件环境：

EDA软件：Vivado2019
实验开发板：Basys3 FPGA套件

二、实验内容：

　　实现的电路功能为：实验板上的四个按键对应四个led灯，按键按下，对应的led灯点亮；几个按键按下则有几个对用的led灯点亮。

　　要求分别使用if/else以及case语句进行逻辑功能描述。

三、具体实现

设计源码

if/else语句

 1 `timescale 1ns / 1ps
 2 //////////////////////////////////////////////////////////////////////////////////
 3 // Company: 
 4 // Engineer: 
 5 // 
 6 // Create Date: 2020/08/16 20:31:23
 7 // Design Name: 
 8 // Module Name: led
 9 // Project Name: 
10 // Target Devices: 
11 // Tool Versions: 
12 // Description: 
13 // 
14 // Dependencies: 
15 // 
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 // 
20 //////////////////////////////////////////////////////////////////////////////////
21 
22 
23 module led(
24     input [3:0] key,
25     output reg [3:0] led
26     );
27     
28     always@(key)
29     begin
30         if(key[0] == 1)
31             led[0] = 1;
32         else
33             led[0] = 0;
34         if(key[1] == 1)
35             led[1] = 1;
36         else 
37             led[1] = 0;
38         if(key[2] == 1)
39             led[2] = 1;
40         else 
41             led[2] = 0;
42         if(key[3] == 1)
43             led[3] = 1;
44         else
45             led[3] = 0;
46     end
47     
48 endmodule

View Code

case语句

 1 `timescale 1ns / 1ps
 2 //////////////////////////////////////////////////////////////////////////////////
 3 // Company: 
 4 // Engineer: 
 5 // 
 6 // Create Date: 2020/08/16 20:45:18
 7 // Design Name: 
 8 // Module Name: led
 9 // Project Name: 
10 // Target Devices: 
11 // Tool Versions: 
12 // Description: 
13 // 
14 // Dependencies: 
15 // 
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 // 
20 //////////////////////////////////////////////////////////////////////////////////
21 
22 
23 module led(key, led);
24     input [3:0] key;
25     output reg [3:0] led;
26     
27     always @(key)
28     begin
29         case(key)
30             4'b0001: led = key;
31             4'b0010: led = key;
32             4'b0100: led = key;
33             4'b1000: led = key;
34             default: led = 4'b0000;
35         endcase
36     end
37     
38 endmodule

View Code

仿真代码

 1 `timescale 1ns / 1ps
 2 //////////////////////////////////////////////////////////////////////////////////
 3 // Company: 
 4 // Engineer: 
 5 // 
 6 // Create Date: 2020/08/17 09:51:40
 7 // Design Name: 
 8 // Module Name: led_tb
 9 // Project Name: 
10 // Target Devices: 
11 // Tool Versions: 
12 // Description: 
13 // 
14 // Dependencies: 
15 // 
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 // 
20 //////////////////////////////////////////////////////////////////////////////////
21 
22 
23 module led_tb;
24     reg [3:0] key;
25     wire [3:0] led;
26     
27     led uut(.key(key), .led(led));
28     
29     initial
30     begin
31         key = 4'b0000;
32         
33         #100 key = 4'b0001;
34         #100 key = 4'b0000;
35         #50 key = 4'b0010;
36         #50 key = 4'b0100;
37         #50 key = 4'b1000;
38         #50 key = 4'b1111;
39         #50 $stop;
40     end
41 endmodule

View Code

波形图

约束文件

 1 set_property PACKAGE_PIN V17 [get_ports key[0]]
 2 set_property IOSTANDARD LVCMOS33 [get_ports key[0]]
 3 set_property PACKAGE_PIN V16 [get_ports key[1]]
 4 set_property IOSTANDARD LVCMOS33 [get_ports key[1]]
 5 set_property PACKAGE_PIN W16 [get_ports key[2]]
 6 set_property IOSTANDARD LVCMOS33 [get_ports key[2]]
 7 set_property PACKAGE_PIN W17 [get_ports key[3]]
 8 set_property IOSTANDARD LVCMOS33 [get_ports key[3]]
 9 set_property PACKAGE_PIN U16 [get_ports led[0]]
10 set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
11 set_property PACKAGE_PIN E19 [get_ports led[1]]
12 set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
13 set_property PACKAGE_PIN U19 [get_ports led[2]]
14 set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
15 set_property PACKAGE_PIN V19 [get_ports led[3]]
16 set_property IOSTANDARD LVCMOS33 [get_ports led[3]]

View Code