module test(KEY_UP,SEL,DIG,CLOCK,RESET);
input KEY_UP,CLOCK,RESET;
output [5:0] SEL;
output reg [7:0] DIG;
parameter cnt=23'd2_000_000;
reg [22:0] cnt1;
reg [31:0] count;
reg t;
wire b;
always @ (posedge CLOCK or negedge RESET)
begin
if(!RESET)
t<=1;
else if(!KEY_UP)
t<=0;
else
t<=1;
end
assign b=t;
always @ (posedge CLOCK or negedge RESET)
begin
if(!RESET)
begin
DIG<=8'hc0;
cnt1<=0;
count<=0;
end
else if(!t)
begin
cnt1<=cnt1+1;
if(cnt1==cnt)
begin
count<=count+1;
if(count>=9)
count<=0;
case(count)
0:DIG<=8'hc0;
1:DIG<=8'hf9;
2:DIG<=8'ha4;
3:DIG<=8'hb0;
4:DIG<=8'h99;
5:DIG<=8'h92;
6:DIG<=8'h82;
7:DIG<=8'hf8;
8:DIG<=8'h80;
default:DIG<=8'h90;
endcase
end
end
else
cnt1<=0;
end
assign SEL=8'hfe;
//assign DIG=8'h90;
endmodule