Quartus prime16.0 组合逻辑always块中敏感向量表不全

前言

组合逻辑always块中向量敏感表不全导致的警告。

流程

1.对于如下代码块：

 1 always @(nstate /*or master_din or master_dout_reg*/) begin
 2     //initial;
 3     master_din_reg = 0;
 4     master_dout = 0;
 5     cs = 1'b0;
 6     wr_done = 1'b0;
 7     rd_done = 1'b0;
 8     sck_en = 1'b0;
 9     case (nstate)
10         IDEL: begin
11             cs = 1'b1;
12             wr_done = 1'b0;
13             rd_done = 1'b0;
14         end 
15         LOAD: begin
16             cs = 1'b0;
17             master_din_reg = master_din;
18         end
19         SEND: begin
20             sck_en = 1'b1;
21         end
22         FINISH: begin
23             cs = 1'b1;
24             wr_done = 1'b1;
25             rd_done = 1'b1;
26             sck_en = 1'b0;
27             master_dout = master_dout_reg;
28         end
29         default: begin
30             master_din_reg = 0;
31             master_dout = 0;
32             cs = 1'b0;
33             wr_done = 1'b0;
34             rd_done = 1'b0;
35             sck_en = 1'b0;
36         end
37     endcase //case
38 end

对于master_din和变量master_dout_reg，两者在组合always块中使用读取，但没有在敏感向量表中，将会导致如下错误：

Warning (10235): Verilog HDL Always Construct warning at spi_ms.v(149): variable "master_din" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at spi_ms.v(159): variable "master_dout_reg" is read inside the Always Construct but isn't in the Always Construct's Event Control

2.解决方法是补全敏感向量表，避免产生不必要的锁存器：

 1 always @(nstate or master_din or master_dout_reg) begin
 2     //initial;
 3     master_din_reg = 0;
 4     master_dout = 0;
 5     cs = 1'b0;
 6     wr_done = 1'b0;
 7     rd_done = 1'b0;
 8     sck_en = 1'b0;
 9     case (nstate)
10         IDEL: begin
11             cs = 1'b1;
12             wr_done = 1'b0;
13             rd_done = 1'b0;
14         end 
15         LOAD: begin
16             cs = 1'b0;
17             master_din_reg = master_din;
18         end
19         SEND: begin
20             sck_en = 1'b1;
21         end
22         FINISH: begin
23             cs = 1'b1;
24             wr_done = 1'b1;
25             rd_done = 1'b1;
26             sck_en = 1'b0;
27             master_dout = master_dout_reg;
28         end
29         default: begin
30             master_din_reg = 0;
31             master_dout = 0;
32             cs = 1'b0;
33             wr_done = 1'b0;
34             rd_done = 1'b0;
35             sck_en = 1'b0;
36         end
37     endcase //case
38 end

3.更懒的方式为直接：always @（*）

解决一切问题。

以上。