Quartus14.1中Qsys创建custom component时编译出错原因

利用Quartus14.1中Qsys工具新建自定义组件时会产生“part-select direction is opposite from prefix index direction”错误，这是由于Qsys生成自定义组件的地址空间时没有考虑hw.tcl文件中限定的地址空间范围，而是按照可用的最大地址空间进行分配导致的。

例如我的自定义组件使用PAD0进行通道选择，而Qsys为PAD0分配了可用的最大地址空间，和其他组件地址空间发生了重叠。

localparam ADDR_RANGE = 64'h40000;//最大地址空间

1     localparam PAD0 = log2ceil(64'h40000 - 64'h0); //地址空间错误
2     localparam PAD1 = log2ceil(64'h10008 - 64'h10000); 
3     localparam PAD2 = log2ceil(64'h10050 - 64'h10040); 
4     localparam PAD3 = log2ceil(64'h10090 - 64'h10080); 
5     localparam PAD4 = log2ceil(64'h100d0 - 64'h100c0); 
6     localparam PAD5 = log2ceil(64'h20008 - 64'h20000);

1     localparam ADDR_RANGE = 64'h40000;
2     localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
3     localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
4                                   (RANGE_ADDR_WIDTH == 0) ?
5                                         PKT_ADDR_H :
6                                         PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
7 
8     localparam RG = RANGE_ADDR_WIDTH-1;

1  if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0   ) begin //编译错误在此产生
2             src_channel = 8'b100000;
3             src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
4  end

在计算通道选择时RG的值小于PAD0，这样会导致编译器输出“part-select direction is opposite from prefix index directio”错误（见参考文献2）。

解决方法：

修改

//修正对应的PAD*地址
localparam PAD0 = log2ceil(64'h10000 - 64'h0);

参考文献：

1.http://www.alterawiki.com/wiki/New_Qsys_Issues中Merlin Address Routers for Custom peripherals，内容如下：

Merlin Address Routers for Custom peripherals
Issue: When generating the system, Merlin address routers are generated ignoring the ExplicitAddressSpan Avalon property. This causes channels to be greater than the complete address space in some cases; for instance, for a system that uses 29 bits of address space (512 MBs), with explicitly using only 16 MBs, Merlin address routers are generated with full 29 bits of address space per channel. Since the complete address space defaults to the size of the address space of the biggest addressable peripheral, this later causes errors in compilation (Verilog errors containing "...part-select direction is opposite from prefix index direction...") and also address space is overlapped with other peripherals with smaller address spaces.
Workaround: Manually edit nios_addr_router.sv files (there will be more of them; they are located under {nios_name}synthesissubmodules directory in your project directory) and manually set the values of the PADx variables to the desired address space size (ExplicitAddressSpanValue = 2^PADxValue). Do not change the value of the complete address space (RG variable), as this might introduce more problems.

2.http://quartushelp.altera.com/14.0/mergedProjects/msgs/msgs/evrfx2_veri_opposite_direction.htm，内容如下：

Verilog HDL error at <location>: part-select direction is opposite from prefix index direction

(ID: 13437)
CAUSE:
In a Verilog Design File (.v) at the specified location, you used a part-select to select a part of a vector; however, in the part-select, the direction from MSB to LSB is reversed from the direction in the declaration of the vector. For example, see the following excerpt of a sample design, which uses a part-select on vector:
module veri_test(in, out);
   input [3:0] in;
   output [1:0] out;
   assign out = in[0:1];
	endmodule
ACTION:
Use the same direction in the part-select of a vector as is used in the declaration of the vector. For example, in the previous sample design, you can change the assignment to out into the following format:
assign out = in[1:0];
See also:

Section 4 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

Quartus14.1中Qsys创建custom component时编译出错原因

Verilog HDL error at <location>: part-select direction is opposite from prefix index direction