CMOS logic is a newer technology, based on the use of complementary MOS transistors to
perform logic functions with almost no current required. [1] This makes these gates very useful in
battery-powered applications. The fact that they will work with supply voltages as low as 3 Volts
and as high as 15 Volts is also very helpful.
CMOS gates are all based on the fundamental inverter circuit
shown in Fig. 3.1. Note that both transistors are enhancement- mode
MOSFETs; one N-channel with its source grounded, and one
P-channel with its source connected to ＋V. Their gates are connected
together to form the input, and their drains are connected together to
form the output.
The two MOSFETs are designed to have matching characteristics.
Thus, they are complementary to each other. When off, their resistance is effectively infinite;
when on, their channel resistance is about 200Ω. Since the gate is essentially an open circuit, it
draws no current, and the output voltage will be equal to either ground or to the power supply
voltage, depending on which transistor is conducting.
When input A is grounded (logic 0) , the N-channel MOSFET is unbiased, and therefore has
no channel enhanced within itself. It is an open circuit, and therefore leaves the output line
disconnected from ground. At the same time, the P-channel MOSFET is forward biased, so it has
a channel enhanced within itself. This channel has a resistance of about 200Ω, connecting the
output line to the ＋V supply. This pulls the output up to ＋V (logic 1).
When input A is at ＋V (logic 1) , the P-channel
MOSFET is off and the N-channel MOSFET is on, thus
pulling the output down to ground (logic 0). Thus, this circuit
correctly performs logic inversion, and at the same time
provides active pull-up and pull-down, according to the
output state.
This concept can be expanded into NOR and NAND
structures by combining inverters in a partially series,
partially parallel structure. The circuit shown in Fig. 3.2 is a
practical example of a CMOS 2-input NOR gate.
In this circuit, if both inputs are low, both P-channel
MOSFETs will be turned on, thus providing a connection to
＋V. Both N-channel MOSFETs will be off, so there will be
no ground connection. However, if either input goes high, that P-channel MOSFET will turn off
and disconnect the output from ＋V, while that N-channel MOSFET will turn on, thus
grounding the output.
The structure can be inverted, as shown in Fig. 3.3. Here
we have a two-input NAND gate, where a logic 0 at either
input will force the output to logic 1, but it takes both inputs at
logic 1 to allow the output to go to logic 0. [2]
This structure is less limited than the bipolar equivalent
would be, but there are still some practical limits. One of these
is the combined resistance of the MOSFETs in series. As a
result, CMOS totem poles are not made more than four inputs
high. Gates with more than four inputs are built as cascading
structures rather than single structures. However, the logic is
still valid.
Even with this limit, the totem pole structure still causes
some problems in certain applications. The pull-up and pull-down resistances at the output are
never the same, and can change significantly as the inputs change state, even if the output does
not change logic states. The result is uneven and unpredictable rise and fall times for the output
signal. This problem was addressed, and was solved with the buffered, or B-series CMOS gates.
The technique here is to follow the actual NAND gate with a pair of inverters, as shown in
Fig. 3.4. Thus, the output will always be driven by a single transistor, either P- channel or
N-channel. Since they are as closely matched as possible, the output resistance of the gate will
always be the same, and signal behavior is therefore more predictable.
One of the main problems with CMOS gates is their speed. They cannot operate very
quickly, because of their inherent input capacitance. B-series devices help to overcome these
limitations to some extent, by providing uniform output current, and by switching output states
more rapidly, even if the input signals are changing more slowly.
Note that we haven’t gone into all of the details of CMOS gate construction here. For
example, to avoid damage caused by static electricity, different manufacturers developed a
number of input protection circuits to prevent input voltages from becoming too high. [3]
However, these protection circuits don’t affect the logical behavior of the gates, so we won’t go
into the details here.
CMOS 逻辑电路是一种基于互补MOS 型晶体管来完成逻辑运算的新技术，工作时几
乎不需要电流。因此，这些门在电池供电的应用中十分有用。它们可以在低到3 伏、高到
15 伏的电压范围内工作，这也有助于实际应用。
CMOS 门都是基于如图3.1 所示的基本非门电路。注意两只管子都是增强型的
MOSFET，一只是源极接地的N 沟道管子，一只是源极接电源正极的P沟道管子。其栅极
连在一起构成输入，漏极连在一起构成输出。
两只MOSFET 具有互相匹配的特性，二者是互补的。在截止时，其电阻为无穷大，而
导通时的通道电阻约为200 欧。由于栅极实际上是开路的，因此不吸收电流。输出电压不
为0就等于电源电压，取决于哪只管子导通。
当输入A 接地时(逻辑0)，N 沟道MOSFET 没有偏置，其中就没有沟道导通。由于管
子开路，因此使输出与地断开。同时，P 沟道MOSFET正偏，其沟道导通。该沟道的电阻
约为200 欧，将输出接到电源正极上(逻辑1)。
当输入A接到电源正极时(逻辑1)，P 沟道MOSFET截止而N沟道MOSFET 导通，因
此将输出拉低为地(逻辑0)。这样，该电路正好实现了逻辑非的功能，同时还根据输出的状
态提供有源的上拉或下拉。
通过把非门连接成部分串联、部分并联的结构，可将这种思想扩展到或非和与非结构。
如图3.2 中所示的电路为CMOS型两输入或非门的实例。
如果该电路中的两个输入都为低，两个P 沟道MOSFET都将导通，这样就接到电源的
正极上。两个N 沟道MOSFET 都将截止，因此就不会与地接通。然而，如果任一个输入
变高，P 沟道MOSFET 就截止，并断开与电源正极的连接，而N 沟道MOSFET 将导通，
将输出接地。
该电路可以颠倒结构顺序，如图3.3 所示。这是一个两输入的与非门，任一输入的逻
辑0都会使输出为逻辑1，但只有两个输入都为逻辑1 时才会使输出变为逻辑0。
这种结构比同等功能的双极性电路更灵活一些，但还存在一些实际的限制。限制之一
就是串联连接的MOSFET的复合电阻。因此，CMOS 图腾柱的高电平输入最多不会超过4
个。输入多于4 个的门设计成级联的形式，而不会采用单一的结构。当然，其逻辑功能仍
然是有效的。
即使在这种限制下，图腾柱结构在某些特定的应用中还会带来一些问题。输出的上拉
电阻和下拉电阻永远不一样，并且即使输出的逻辑状态不变，在输入改变状态时电阻会变
化很大。其结果是输出出现不确定的上下反复变化。这个问题通过缓冲器或B系列的CMOS
门处理可以得到解决。
如图3.4 所示，处理方法是在实际的与非门后加一对反相器。这样，输出就总是由N
沟道或P 沟道管子中的一只管子来驱动。由于它们尽可能互相匹配，门电路的输出电阻就
总是一样的，信号的特性也因此更加确定。
CMOS 门的一个主要问题是工作速度。由于固有的输入电容的影响，它们不可能工作
得很快。通过提供同样的输出电流并快速切换输出状态，即使输入信号变化缓慢，B 系列
器件也在一定程度上克服了这些局限性。
应该说明的是，这里并没有探讨CMOS门电路的技术细节。例如，为了避免静电的损
坏，各个制造商都开发了各种输入保护电路来防止输入电压变得过高。不过，这些保护电
路并不影响门电路的逻辑特性，这里我们就不详细讨论了。