cyclone系列IO问题转自altera网站

cyclone系列的IO特性：

1.可编程电流驱动能力
2.可编程信号斜率控制
3.开漏设置
4.可编程总线保持
5.上啦电阻
6.PCI钳位二极管
7.片上终端电阻
8.可编程延迟

Programmable I/O Features of the Cyclone FPGA Series

The Cyclone^? FPGA series offers a variety of programmable I/O features that are easily implemented using Quartus^? II software. This page provides general programmable I/O feature guides, such as when and how to use them, their availability, and their limitations. Also included is information on how each setting affects the interface or design. Following are the key programmable I/O features:

Note:
Programmable I/O-related settings are typically made in the Assignment Editor environment. However, for a variety of reasons, some of these settings may be automatically changed or ignored during the fitting process. Although you are notified of each change with a warning or information message, these messages can easily be missed, especially in large designs. Check the fitter report section to verify that your desired settings have been successfully implemented after compilation flow. The I/O-related settings are reported within sub-sections of the input pins, output pins, bidir pins, and delay chain summaries.

For detailed information on the architecture and specifications for each programmable I/O feature, refer to the respective device handbooks:

Programmable Current Strength

When to Use

Current strength affects output performance (f_MAX, tco) and signal quality (edge rate, voltage overshoot and undershoot, and noise).
A higher current strength setting provides increased output performance but also larger noise levels
When not selected, the default setting varies by family within the Cyclone FPGA series as follows:
- Cyclone and Cyclone II FPGAs—maximum setting for each I/O standard.
- Cyclone III FPGAs—50-Ohm on-chip termination (OCT) without calibration for all non-voltage reference and HSTL/SSTL; Class I I/O standkehout calibration for HSTL/SSTL; Class II I/O standards—maximum setting for 3.3-V LVTTL/LVCMOS I/O standards.
When a higher f_MAX is required for the output and timing violation on minimum pulse width is encountered, choose a higher valid current strength setting.

How to Use

In the Assignment Editor, choose an available current setting for the pin. Maximum and minimum values denote the largest and smallest valid current strength setting, respectively, supported by the I/O standard.

Feature Availability

All user I/Os are used as output or bidirectional pins.
Current strength choices vary with device family and I/O standards.

Feature Limitations

Not supported in dedicated configuration pins.
Not available in pins that are using OCT with or without calibration.

Programmable Slew Rate Control

When to Use

Slew rate affects the transition edge rate of the output signal, output performance (f_MAX, tco), and switching noise, especially when a large number of output pins switch simultaneously.
When noise factor is critical in your system, choose a slower valid slew rate setting.
When not selected, Quartus II software is set to the fastest valid slew rate control.

How to Use

In the Assignment Editor, select the desired value per the pin assignment.
Assignment name and values for Cyclone series families are as follows:

FPGA Family	Assignment Name	Assignment Value
Cyclone	Slow Slew Rate	ON (slow)
		OFF (fast - default)
Cyclone III	Slew Rate	0 (slow)
		1 (medium)
		2 (fast - default)

Feature Availability

All user I/Os are used as output or bidirectional pins.
Can be used along with programmable current strength.

Feature Limitations

Not supported in dedicated configuration pins.
Not available in pins that are using OCT with calibration.
Not available for the Cyclone II FPGA family. Refer to support solution rd02222005_115.
Only supported for current strength settings of 8 mA or above in Cyclone III FPGAs because at lower current settings, the edge rate effect is insignificant.
Not available in pins that are using 3.0-V PCI and 3.0-V PCI-X I/O standards in Cyclone III FPGAs.

Programmable Open-Drain Output

When to Use

An open-drain output provides a high-impedance state on output when logic-to-pin is high. If logic-to-pin is low, output is low.
More than one open-drain output can be attached to a single wire. This type of connection is analogous to a logical OR function and is commonly termed as an active-low wired-OR circuit. If at least one of the outputs is in the logic 0 state (active), it sinks the current and brings the line to low voltage.
Use when connecting multiple devices to a bus. For example, system-level control signals that can be asserted by any device or as an interrupt.

How to Use

There are two ways to enable the open-drain output assignment:
- OPNDRN primitive—Design the tri-state buffer with an OPNDRN primitive. The input to the primitive is equivalent to the Output Enable (OE) signal when using a TRI primitive.
- Auto Open-Drain Pins option—This is a global setting that directs the compiler to automatically convert a tri-state buffer (usually with TRI primitive) with a fixed low data input into the equivalent open-drain buffer throughout the design. This option is enabled by default.
You can design open-drain output without enabling the option assignment. In that case, you are not utilizing the open-drain output feature in the I/O buffer. Using the open-drain output feature in the I/O buffer provides you the best propagation delay, tpd from OE to output.
Support solution rd06252007_878 shows an example of how you can implement the open-drain output using standard VHDL or Verilog HDL statements.

Feature Availability

All user I/Os are used as output or bidirectional pins.
Can be used along with programmable pull-up resistor.

Feature Limitation

Not available in dedicated configuration pins.

Programmable Bus Hold

When to Use

Use when there is a need to hold the last-driven state of the pin until the next input signal is present, which usually happens when the pin is tri-stated.
Putting pins in a known voltage level with the bus hold feature avoids unintended switching due to noise.

How to Use

In the Assignment Editor, set the bus hold assignment to ON to enable the bus hold circuitry for the pin.

Feature Availability

All user I/Os.

Feature Limitations

Not supported in dedicated configuration pins and dedicated clock input pins.

Programmable Pull-up Resistor

When to Use

Use when there is a need to pull a pin signal level to V_CCIO when it is tri-stated.
Use to replace a weak external pull-up resistor. The pull-up resistance varies with process, voltage, and temperature conditions.
Use external components if you require precision values.
Use in combination with open-drain output option.

How to Use

In the Assignment Editor, set the weak pull-up assignment to ON to enable the on-chip pull-up resistor for the pin.

Feature Availability

All user I/Os.

Feature Limitations

Not supported in dedicated configuration pins and dedicated clock input pins.
Not available in pins that are using bus hold option.

PCI-Clamp Diode

When to Use

A PCI diode-enabled pin only affects signal voltage about 0.7 V above V_CCIO level. Higher voltage levels are clipped, effectively reducing voltage level at pin to about V_CCIO + 0.7-V level. 0.7 V is an approximation of the on-chip diode turn-on voltage.
Use when the voltage overshoot seen at the FPGA pin exceeds acceptable maximum level. FPGAs in the Cyclone family have maximum DC input and maximum overshoot (AC) voltage specifications.
Use when interfacing a Cyclone II FPGA or a Cyclone FPGA with a 5.0-V LVTTL device to clamp voltage at the FPGA pin to an acceptable maximum level.
For all cases of usage, determine if series resistor is needed to reduce DC current to acceptable limit through the on-chip diode.

How to Use

In the Assignment Editor, set the PCI I/O assignment to ON to enable the on-chip clamp diode for the pin.

Feature Availability

All banks of user I/O pins for Cyclone III FPGAs.
Only with side bank user I/O pins for Cyclone II and Cyclone FPGAs.

Feature Limitations

Not supported in dedicated input clock and configuration pins.
There is a maximum of 10-mA DC current through the on-chip clamp diode for Cyclone III FPGAs and 25- mA for Cyclone II and Cyclone FPGAs.
Not available in dual-purpose configuration pins that are used during configuration for FPGAs in the Cyclone III family.

On-Chip Termination

When to Use

An OCT output pin provides on-chip impedance matching capability to a 25-ohm or 50-ohm trace to reduce reflections-induced noise on the signal.
Use OCT with calibration in Cyclone III FPGAs for higher calibration accuracy to account for temperature and voltage condition variations.

How to Use

In the Assignment Editor, from I/O standard assignments, select from a list of available OCT I/O standards. Valid choices are 25-ohm or 50-ohm termination type, at various V_CCIO levels, and with a calibration option.
When using series OCT with calibration on a pin, the RUP pin and RDN pin in the same side bank where the target pin resides must be connected to an external resistor, and each tied to V_CCIO and GND, respectively. Use a 25-ohm resistor for 25-ohm termination type, and a 50-ohm resistor for 50-ohm termination type.
When using series OCT without calibration, an external resistor to the RUP and RDN pins is not required. In that case, the RUP and RDN pins can be used as regular I/O.

Feature Availability

Use series OCT with and without calibration in Cyclone III FPGAs on all user I/Os used as output and bidirectional pins.
Use series OCT without calibration in Cyclone II FPGAs on all user I/Os used as output and bidirectional pins.
When OCT is used with bidirectional pins, resistance in series at the pin does not exist when the pin is an input.

Feature Limitations

Not supported in dedicated configuration pins.
OCT is not supported for 3.3-V LVTTL/LVCMOS I/O standard in the Cyclone III FPGA family.
OCT with calibration is not supported in the Cyclone II FPGA family.
There is no OCT support, with or without calibration, in the Cyclone FPGA family.

Programmable Delay

When to Use

A delay setting in an I/O path affects the timing requirement on that pin. Use programmable delay to improve the read or write timing in an interface.
The figure shows an example of hold time improvement for the input register with the use of input pin to input register delay.

How to Use

Delays associated with registers are only usable if the registers are placed in the IOE. You can direct the compiler using the Assignment Editor by turning the Fast Input Register or Fast Output Register assignment for the input register or output register to ON.
Quartus II development software automatically programs these delays if you constrain the input or output port. Use the set_input_delay or set_output_delay command with the TimeQuest timing analyzer. Or, use the classic timing analyzer to make the input delay or output delay assignment to optimize delay settings and logic placements to meet your constraints, and to analyze and report timing results.
In Quartus II software, the pad to input register delay is set to the maximum by default. To manually edit the delays, set an integer value to the respective delay assignment in the Assignment Editor. Valid integer values and associated incremental offset delay can be referenced in the respective device handbooks.
The actual delay values = integer value x (maximum offset value referenced in the device handbook)/(number of settings available for the delay - 1).
If you need to fine-tune the delay after a compilation, you can do so without full recompilation by editing the delay from the resource property editor.

Feature Availability

All user I/Os.

Feature Limitation

Not supported in dedicated configuration pins.