当某信号没有在Top Level上被使用，但又希望其出现在SignalTap II中作为测试信号，除了把该信号在顶层中声明为port之外，还可以利用编译器的synthesis attribute。具体方法如下：
1、当被保留的信号为wire类型
wire net1/*synthesis keep*/;
2、当被保留的信号为reg类型
reg reg1/*synthesis noprune*/;
3、当保留的reg没有fanout
reg reg1/*synthesis preserve*/;
若一个reg没有fanout，它会被直接接到VCC或GND
说明：
1、noprune与preserve的区别
按照Qii help的说法http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_noprune.htm
noprune与preserve的区别为：
(noprune is)A Verilog HDL synthesis attribute that prevents the Quartus II software from removing a register that does not directly or indirectly feed a top-level output or bidir pin, such as a fanout-free register. This attribute differs from the preserve attribute, which only prevents a register from being reduced to a constant or merged with a duplicate register.
另外，还可以用以下方法实现noprune:
You can also use Verilog 2001 attribute syntax to preserve a fanout-free register, as shown in the following code:
(* noprune *) reg reg1;
2、keep引入的小偏移
keep会在时序路径上增加一个逻辑单元的延时
Note that adding "keep" may add one logic cell delay in your timing path (probably not a problem, but something to keep in mind if it is a timing-critical path).
3、未经验证的说法
/*synthesis keep*/也支持对reg型信号，使用它也可以防止reg型信号被优化掉。但是也有可能出现这样的情况，有的信号即使经过此处理，仍然会被综合工具优化掉，致使无法找到它。这个时候就需要对其使用“测试属性”，可以加入probe_port属性，把这两个属性结合在一起，即就是：
( *synthesis, probe_port,keep *) 即可，这种方法同时适应于wire和reg型信号类型。