仿真altera或者xilinx的ip核

第一步:在modelsim里新建个library 如altera_mf_ver(altera_mf.v),lpm_ver(220model.v)
第二步:编译altera里的库文件 一般在C:\altera\81\quartus\eda\sim_lib\目录下的220model.v和altera_mf.v
第三步: compile
第四步:修改modelsim安装目录下的modelsim.ini
[Library]
my_lib 
= c:/my_lib

; Altera specific primitive library mappings 
vital2000 
= $MODEL_TECH/../vital2000
ieee 
= $MODEL_TECH/../ieee
verilog 
= $MODEL_TECH/../verilog
std 
= $MODEL_TECH/../std
std_developerskit 
= $MODEL_TECH/../std_developerskit
synopsys 
= $MODEL_TECH/../synopsys

这样每次一打开modelsim就有altera的库了


ModelSim 加入Xilinx library

在C:\Modeltech_6.0\下建立Xilinx_Lib的目錄, 命令提示字元切到C:\Xilinx91i\bin\nt
執行#C:\Xilinx91i\bin\nt>compxlib -s mti_se -f all -o c:\Modeltech_6.0\Xilinx_Lib -p c:\Modeltech_6.0\win32

編輯C:\Xilinx91i\bin\nt\modelsim.ini

UNISIMS_VER = c:\Modeltech_6.0\Xilinx_Lib\unisims_ver
UNI9000_VER = c:\Modeltech_6.0\Xilinx_Lib\uni9000_ver
SIMPRIMS_VER = c:\Modeltech_6.0\Xilinx_Lib\simprims_ver
XILINXCORELIB_VER = c:\Modeltech_6.0\Xilinx_Lib\XilinxCoreLib_ver
AIM_VER = c:\Modeltech_6.0\Xilinx_Lib\abel_ver\aim_ver
CPLD_VER = c:\Modeltech_6.0\Xilinx_Lib\cpld_ver
UNISIM = c:\Modeltech_6.0\Xilinx_Lib\unisim
SIMPRIM = c:\Modeltech_6.0\Xilinx_Lib\simprim
XILINXCORELIB = c:\Modeltech_6.0\Xilinx_Lib\XilinxCoreLib
AIM = c:\Modeltech_6.0\Xilinx_Lib\abel\aim
PLS = c:\Modeltech_6.0\Xilinx_Lib\abel\pls
CPLD = c:\Modeltech_6.0\Xilinx_Lib\cpld

原文地址:https://www.cnblogs.com/fpga/p/1570041.html