此部分其实很简单，应用了上述边沿检测的部分思维，用最高时钟打慢几拍，便实现了与最高时钟的同步。此处不再用Block来累赘的描述，verilog设计代码如下所示：
/*****************************************************
* Module Name : synchronism_design.v
* Engineer : Crazy Bingo
* Target Device : EP2C8Q208C8
* Tool versions : Quartus II 11.0
* Create Date : 2011-6-25
* Revision : v1.0
* Description :
*****************************************************/
module synchronism_design
(
input clk,
input rst_n,
output sys_rst_n
);
//------------------------------------------
//rst_n synchronism, is controlled by the input clk
reg rst_nr1, rst_nr2;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rst_nr1 <= 1'b0;
rst_nr2 <= 1'b0;
end
else
begin
rst_nr1 <= 1'b1;
rst_nr2 <= rst_nr1;
end
end
assign sys_rst_n = rst_nr2; //active low
endmodule