功能覆盖率的类型
在验证计划中编写test case时，需要编写功能覆盖率计划。一般而言，在验证环境中有4个地方可以编写coverage points.
F1 : Functional coverage points are very near the randomization
F2 : Functional coverage points are sampled at input interface of DUT
F3 : Functional coverage points which sample internal DUT states
F4 : Functional coverage points which sample output interface of DUT
功能覆盖率的简单例子：
1 //+++++++++++++++++++++++++++++++++++++++++++++++++ 2 // DUT With Coverage 3 //+++++++++++++++++++++++++++++++++++++++++++++++++ 4 module simple_coverage(); 5 6 logic [7:0] addr; 7 logic [7:0] data; 8 logic par; 9 logic rw; 10 logic en; 11 //================================================= 12 // Coverage Group 13 //================================================= 14 covergroup memory @ (posedge en); 15 address : coverpoint addr { 16 bins low = {0,50}; 17 bins med = {51,150}; 18 bins high = {151,255}; 19 } 20 parity : coverpoint par { 21 bins even = {0}; 22 bins odd = {1}; 23 } 24 read_write : coverpoint rw { 25 bins read = {0}; 26 bins write = {1}; 27 } 28 endgroup 29 //================================================= 30 // Instance of covergroup memory 31 //================================================= 32 memory mem = new(); 33 //================================================= 34 // Task to drive values 35 //================================================= 36 task drive (input [7:0] a, input [7:0] d, input r); 37 #5 en <= 1; 38 addr <= a; 39 rw <= r; 40 data <= d; 41 par <= ^d; 42 $display ("@%2tns Address :%d data %x, rw %x, parity %x", 43 $time,a,d,r, ^d); 44 #5 en <= 0; 45 rw <= 0; 46 data <= 0; 47 par <= 0; 48 addr <= 0; 49 rw <= 0; 50 endtask 51 //================================================= 52 // Testvector generation 53 //================================================= 54 initial begin 55 en = 0; 56 repeat (10) begin 57 drive ($random,$random,$random); 58 end 59 #10 $finish; 60 end 61 62 endmodule
In the example we have covergroup memory which basically gets sampled on every posedge of en, and it samples address for three ranges, parity for even and odd, and finally rw for read and write.
和module/program/interface, coverage 可以用new()实例化，在每个en的边沿上所有的数据被采样存储在仓库（bins）中。
编写Makefile 文件
all:
vcs -sverilog -R simple_voerage.sv -debug_all
cov:
dve -covdir simv.vdb&
urg:
urg -dir simv.vdb
clean:
rm -rf *.log simv.* DVEfiles urg* csrc *.key simv
首先，运行make all 生成覆盖率文件simv.vdb文件，然后运行make dve，用dve图形化的方式查看代码覆盖率。
参考文献：
[1] http://www.asic-world.com/systemverilog/coverage1.html#Simulation_:_Coverage