Optimizing Physical Implementation and Timing Closure
Planning Physical Implementation
When planning a design, consider the following elements of physical implementation:
• The number of unique clock domains and their relationships
• The amount of logic in each functional block
• The location and direction of data flow between blocks
• How data routes to the functional blocks between I/O interfaces
When adding register stages to pipeline control signals, turn off the Auto Shift Register Replacement
option (Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis)) for these registers. By default, chains of registers can be converted to a RAM-based implementation based on
performance and resource estimates.
Planning FPGA Resources
Plan functional blocks with appropriate global, regional, and dual-regional network signals in mind.
When floorplanning a design, consider the balance of different types of device resources, such as memory, logic, and DSP blocks in the main functional blocks.
Optimizing Timing Closure
You can use physical synthesis optimizations for combinational logic, register retiming, and register duplication techniques to optimize your design for timing closure.
Click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) to turn on physical
synthesis options.
• Physical synthesis for combinational logic—When the Perform physical synthesis for combinational logic is turned on, the report panel identifies logic that physical synthesis can modify. You can use this information to modify the design so that the associated optimization can be turned off to save compile time.
• Register duplication—This technique is most useful where registers have high fan-out, or where the fan-out is in physically distant areas of the device. Review the netlist optimizations report and consider manually duplicating registers automatically added by physical synthesis. You can also locate the original and duplicate registers in the Chip Planner. Compare their locations, and if the fan-out is improved, modify the code and turn off register duplication to save compile time.
• Register retiming—This technique is particularly useful where some combinatorial paths between registers exceed the timing goal while other paths fall short. If a design is already heavily pipelined, register retiming is less likely to provide significant performance gains since there should not be significantly unbalanced levels of logic across pipeline stages.
The application of appropriate timing constraints is essential to timing closure. Use the following
general guidelines in applying timing constraints:
• Apply multicycle constraints in your design wherever single-cycle timing analysis is not required.
• Apply False Path constraints to all asynchronous clock domain crossings or resets in the design. This technique prevents overconstraining and the Fitter focuses only on critical paths to reduce compile time. However, over constraining timing critical clock domains can sometimes provide better timing results and lower compile times than physical synthesis.
• Overconstrain rather than using physical synthesis when the slack improvement from physical
synthesis is near zero. Overconstrain the frequency requirement on timing critical clock domains by using setup uncertainty.
• When evaluating the effect of constraint changes on performance and runtime, compile the design with at least three different seeds to determine the average performance and runtime effects. Different constraint combinations produce various results. Three samples or more establishes a performance trend. Modify your constraints based on performance improvement or decline.• Leave settings at the default value whenever possible. Increasing performance constraints can increase the compile time significantly. While those increases may be necessary to close timing on a design, using the default settings whenever possible minimizes compile time.
Optimizing Critical Timing Paths
Review the register placement and routing paths by clicking Tools > Chip Planner. Large timing failures
on high fan-out control signals can be caused by any of the following conditions:
• Sub-optimal use of global networks
• Signals that traverse the chip on local routing without pipelining
• Failure to correct high fan-out by register duplication
For high-speed and high-bandwidth designs, optimize speed by reducing bus width and wire usage. To reduce wire use, move the data as little as possible.