在编电子表时发现FPGA求余，取模只能针对2的次方。毕竟是数字的嘛！
时钟用到了动态刷新数码管。以一个大于50Hz的速度刷新每一个数码管。
因为数码管只有四个，只写了分针和秒针。
代码如下：
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use IEEE.STD_LOGIC_ARITH.ALL; 4 use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 6 entity clock is 7 Port ( clk : in STD_LOGIC; 8 seg : out STD_LOGIC_VECTOR (6 downto 0); 9 an : out STD_LOGIC_VECTOR (3 downto 0)); 10 end clock; 11 12 architecture Behavioral of clock is 13 signal num:STD_LOGIC_VECTOR (3 downto 0); 14 signal min_h:STD_LOGIC_VECTOR (3 downto 0); 15 signal min_l:STD_LOGIC_VECTOR (3 downto 0); 16 signal second_h:STD_LOGIC_VECTOR (3 downto 0); 17 signal second_l:STD_LOGIC_VECTOR (3 downto 0); 18 signal an_sel:STD_LOGIC_VECTOR (1 downto 0); 19 signal cnt: INTEGER; 20 signal cnt2: INTEGER; 21 signal sclk: STD_LOGIC; 22 constant a:integer :=8; 23 begin 24 process(clk) 25 begin 26 if(clk'event and clk='1') then 27 if(cnt=25000000) then 28 cnt<=0; 29 sclk<=not sclk; 30 else 31 cnt<=cnt+1; 32 end if; 33 end if; 34 end process; 35 36 process(clk) 37 begin 38 if(clk'event and clk='1') then 39 if(cnt2=100000) then 40 cnt2<=0; 41 if(an_sel="11") then 42 an_sel<="00"; 43 else 44 an_sel<=an_sel+'1'; 45 end if; 46 else 47 cnt2<=cnt2+1; 48 end if; 49 end if; 50 end process; 51 52 process(sclk) 53 begin 54 if(sclk'event and sclk='1') then 55 if(second_h="0101" and second_l="1001") then 56 second_h<="0000"; 57 second_l<="0000"; 58 min_l<=min_l+'1'; 59 if(min_h="0101" and min_l="1001") then 60 min_h<="0000"; 61 min_l<="0000"; 62 elsif(min_l="1001") then 63 min_h<=min_h+'1'; 64 min_l<="0000"; 65 end if; 66 elsif(second_l="1001") then 67 second_h<=second_h+'1'; 68 second_l<="0000"; 69 else 70 second_l<=second_l+'1'; 71 end if; 72 end if; 73 end process; 74 75 process(an_sel,second_l,second_h,min_l,min_h) 76 begin 77 case an_sel is 78 when "00"=>an<="0111";num<=second_l; 79 when "01"=>an<="1011";num<=second_h; 80 when "10"=>an<="1101";num<=min_l; 81 when "11"=>an<="1110";num<=min_h; 82 when others=>null; 83 end case; 84 85 case num is 86 when x"0"=>seg<=b"0000001"; 87 when x"1"=>seg<=b"1001111"; 88 when x"2"=>seg<=b"0010010"; 89 when x"3"=>seg<=b"0000110"; 90 when x"4"=>seg<=b"1001100"; 91 when x"5"=>seg<=b"0100100"; 92 when x"6"=>seg<=b"0100000"; 93 when x"7"=>seg<=b"0001111"; 94 when x"8"=>seg<=b"0000000"; 95 when x"9"=>seg<=b"0000100"; 96 when others=>null; 97 end case; 98 end process; 99 end Behavioral;
约束文件如下：
1 NET "clk" LOC = "B8"; 2 NET "an<0>" LOC="K14"; 3 NET "an<1>" LOC="M13"; 4 NET "an<2>" LOC="J12"; 5 NET "an<3>" LOC="F12"; 6 NET "seg<6>" LOC="L14"; 7 NET "seg<5>" LOC="H12"; 8 NET "seg<4>" LOC="N14"; 9 NET "seg<3>" LOC="N11"; 10 NET "seg<2>" LOC="P12"; 11 NET "seg<1>" LOC="L13"; 12 NET "seg<0>" LOC="M12";