Using the SDRAM on Altera’s
DE1-SoC Board with Verilog Designs
1.DE1-SOC Board上SDRAM资源
2.系统架构框图
3.关于SDRAM controller
SDRAM controller能生成SDRAM芯片所需要的信号，但是SDRAM芯片的时钟信号需要外部来提供。
4.DE1-SOC Board---SDRAM Controller参数配置
Memory Profile
Timing---自己直接输入参数即可
5.系统时钟与SDRAM时钟的配置
采用university program提供的IP核：
因为板上的时钟为50MHz,所以reference clock:50MHz,本实验的系统时钟也采用50MHz。
6.搭建Qsys系统
选择Reset vector 和 Exception Vector为new_sdram_controller.s1,即软件程序在SDRAM里面跑。
7.在顶层文件上对Qsys系统进行实例化
module top( new_sdram_controller_wire_addr, // new_sdram_controller_wire.addr new_sdram_controller_wire_ba, // .ba new_sdram_controller_wire_cas_n, // .cas_n new_sdram_controller_wire_cke, // .cke new_sdram_controller_wire_cs_n, // .cs_n new_sdram_controller_wire_dq, // .dq new_sdram_controller_wire_dqm, // .dqm new_sdram_controller_wire_ras_n, // .ras_n new_sdram_controller_wire_we_n, // .we_n sys_sdram_pll_ref_clk_clk, // sys_sdram_pll_ref_clk.clk sys_sdram_pll_sdram_clk_clk ); output [12:0] new_sdram_controller_wire_addr; // new_sdram_controller_wire.addr output [1:0] new_sdram_controller_wire_ba; // .ba output new_sdram_controller_wire_cas_n; // .cas_n output new_sdram_controller_wire_cke; // .cke output new_sdram_controller_wire_cs_n; // .cs_n inout [15:0] new_sdram_controller_wire_dq; // .dq output [1:0] new_sdram_controller_wire_dqm; // .dqm output new_sdram_controller_wire_ras_n; // .ras_n output new_sdram_controller_wire_we_n; // .we_n input sys_sdram_pll_ref_clk_clk; // sys_sdram_pll_ref_clk.clk output sys_sdram_pll_sdram_clk_clk; mem u1 ( .sys_sdram_pll_ref_clk_clk (sys_sdram_pll_ref_clk_clk), // sys_sdram_pll_ref_clk.clk .sys_sdram_pll_ref_reset_reset (1'b0), // sys_sdram_pll_ref_reset.reset .new_sdram_controller_wire_addr (new_sdram_controller_wire_addr), // new_sdram_controller_wire.addr .new_sdram_controller_wire_ba (new_sdram_controller_wire_ba), // .ba .new_sdram_controller_wire_cas_n (new_sdram_controller_wire_cas_n), // .cas_n .new_sdram_controller_wire_cke (new_sdram_controller_wire_cke), // .cke .new_sdram_controller_wire_cs_n (new_sdram_controller_wire_cs_n), // .cs_n .new_sdram_controller_wire_dq (new_sdram_controller_wire_dq), // .dq .new_sdram_controller_wire_dqm (new_sdram_controller_wire_dqm), // .dqm .new_sdram_controller_wire_ras_n (new_sdram_controller_wire_ras_n), // .ras_n .new_sdram_controller_wire_we_n (new_sdram_controller_wire_we_n), // .we_n .sys_sdram_pll_sdram_clk_clk (sys_sdram_pll_sdram_clk_clk) // sys_sdram_pll_sdram_clk.clk ); endmodule
综合结果图：
8.烧写硬件代码开启NIOS II---eclipse
9.编写C语言代码
/* * "Hello World" example. * * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT * device in your system's hardware. * The memory footprint of this hosted application is ~69 kbytes by default * using the standard reference design. * * For a reduced footprint version of this template, and an explanation of how * to reduce the memory footprint for a given application, see the * "small_hello_world" template. * */ #include <stdio.h> #include "system.h" #include "io.h" #include "alt_types.h" int main() { printf("Hello from Nios II! "); alt_u16 i = 0; for(i=0;i<100;i++) { IOWR(0x0, i, i); } return 0; }
关于函数的使用：
9.更新BSP（假设之前更改过硬件）
首先开启BSP Editor，配置相应的部分，最后点击Generate.
9.软件调试 ----Debug
10 读取memory里面的数据
11更改Reset vector 和 Exception Vector为：
即程序在on-chip RAM里面跑。
12.更改了硬件之后，得重新生成BSP
13.BSP做好后，程序就可以开始debug了：
调试结果：读取相应memory里面的数据：
