卷积编码后的删余模块---Verilog代码

卷积编码后的删余模块---Verilog代码

module DATA_conv_encoder(

    input            wire              DCONV_CLK_I,
    input            wire              DCONV_DIN,
    input            wire              DCONV_ND,
    input            wire              DCONV_RST,
    input            wire    [3:0]     RATE_CON,
    input            wire              DCONV_CLK_O,
    output           reg               DCONV_DOUT,
    output           reg     [8:0]     DCONV_INDEX,
    output           reg               DCONV_RDY
);

//-------------------------------------------------------------------------

wire [1:0] DATA_OUT_V;

conv_encoder conv_encoder1(
    .data_in(DCONV_DIN),
    .nd(DCONV_ND),
    .clk(DCONV_CLK_I),
    .aclr(DCONV_RST),
    .data_out_v(DATA_OUT_V),
    .rdy(RDY)
);

//-------------------------------------------------------------------------

reg [1:0] Puncture_BUF_12;   //2
reg [5:0] Puncture_BUF_34;   //6
reg [3:0] Puncture_BUF_23;   //4
reg [1:0] i;
reg BUF_RDY;

always @ ( negedge DCONV_RST or posedge DCONV_CLK_I )
begin
    if(!DCONV_RST)
    begin
       Puncture_BUF_12 <= 0;
        Puncture_BUF_34 <= 0;
       Puncture_BUF_23 <= 0;
       i <= 0;
    end
    else 
    begin
        if(RDY)
        begin
            case(RATE_CON)
            4'b1101,4'b0101,4'b1001:  // Rate is 1/2 .
            begin
                Puncture_BUF_12 <= DATA_OUT_V;
                BUF_RDY <= 1;
            end
            4'b1111,4'b0111,4'b1011,4'b0011:     // Rate is 3/4 .
            begin
                case(i)
                2'b00:
                begin
                    Puncture_BUF_34 [1:0] <= DATA_OUT_V;
                    BUF_RDY <= 1;
                    i <= i + 1 ;
                end
                2'b01:
                begin
                    Puncture_BUF_34 [3:2] <= DATA_OUT_V;
                    BUF_RDY <= 1;
                    i <= i + 1 ;
                end
                2'b10: 
                begin
                    Puncture_BUF_34 [5:4] <= DATA_OUT_V;
                    BUF_RDY <= 1;
                    i <= 2'b00 ;
                end
                default: 
                begin
                    Puncture_BUF_34 <= 0;
                    BUF_RDY <= 0;     
                    i <= 0;
                end
                endcase
            end
            4'b0001:         // Rate is 2/3 .
            begin
                case ( i )
                2'b00:
                begin
                    Puncture_BUF_23 [1:0] <= DATA_OUT_V;
                    BUF_RDY <= 1;
                    i <= i + 1 ;            
                end
                2'b01:
                begin
                    Puncture_BUF_23 [3:2] <= DATA_OUT_V;
                    BUF_RDY <= 1;
                    i <= 0 ;            
                end
                default:
                begin
                    Puncture_BUF_23 <= 0;
                    BUF_RDY <= 0;
                    i <= 0 ;            
                end
                endcase
            end
            endcase
        end
        else 
        begin
            BUF_RDY <= 0;
            Puncture_BUF_12 <= 0;
            Puncture_BUF_34 <= 0;
            Puncture_BUF_23 <= 0;
            i <= 0;
        end
    end
end


//-------------------------------------------------------------------------

reg [2:0] j;

always @ ( negedge DCONV_RST or posedge DCONV_CLK_O )     // Puncture and output the data.
begin
    if(!DCONV_RST)
    begin
        DCONV_DOUT <= 0 ;
        DCONV_RDY <= 0;
        j <= 3'b000;
    end
    else 
    begin
        if(BUF_RDY)
        begin
            case(RATE_CON)
            4'b1101,4'b0101,4'b1001:        // Rate is 1/2 .
            begin
                case (j)
                3'b000:
                begin
                    DCONV_DOUT <= Puncture_BUF_12 [j] ;
                    DCONV_RDY <= 1;
                    j <= j +1 ;
                end
                3'b001:
                begin
                    DCONV_DOUT <= Puncture_BUF_12 [j] ;
                    DCONV_RDY <= 1;
                    j <= 3'b000 ;
                end
                default:
                begin
                    DCONV_DOUT <= 0 ;
                    DCONV_RDY <= 0;
                    j <= 3'b000 ;
                end
                endcase
            end

            4'b1111,4'b0111,4'b1011,4'b0011:     // Rate is 3/4 .
            begin
                case (j)
                3'b000,3'b001,3'b010:
                begin
                    DCONV_DOUT <= Puncture_BUF_34 [j] ;
                    DCONV_RDY <= 1;
                    j <= j + 1 ;
                end              
                3'b011: 
                begin
                    DCONV_DOUT <= Puncture_BUF_34 [j+2] ;
                    DCONV_RDY <= 1;
                    j <= 3'b000 ;
                end
                default: 
                begin
                    DCONV_DOUT <= 0;
                    DCONV_RDY <= 0;     
                    j <= 0;
                end
                endcase
            end 

            4'b0001:         // Rate is 2/3 .
            begin
                case ( j )
                3'b000,3'b001:
                begin
                    DCONV_DOUT <= Puncture_BUF_23 [j] ;
                    DCONV_RDY <= 1;
                    j <= j + 1 ;            
                end
                3'b010:
                begin
                    DCONV_DOUT <= Puncture_BUF_23 [j] ;
                    DCONV_RDY <= 1;
                    j <= 3'b000 ;            
                end
                default:
                begin
                    DCONV_DOUT <= 0 ;
                    DCONV_RDY <= 0 ;
                    j <= 0 ;            
                end
                endcase 
            end
            endcase
        end
        else 
        begin
            DCONV_DOUT <= 0 ;
            DCONV_RDY <= 0 ;
        end
    end
end

//-----------------------------------------------------------------------------

reg [9:0] INDEX_TEMP;
reg [8:0] DCONV_INDEX;

always @ ( negedge DCONV_RST or posedge DCONV_CLK_O )
begin
   if (! DCONV_RST)
   begin
        DCONV_INDEX <= 0 ;
        INDEX_TEMP <= 0;
   end
   else 
   begin
           if(BUF_RDY)
           begin
               case(RATE_CON)
               4'b1101,4'b1111:
            begin
                if(INDEX_TEMP< 47)
                begin
                    INDEX_TEMP <= INDEX_TEMP + 1 ;
                    DCONV_INDEX <= INDEX_TEMP ;
                end
                else
                begin
                    INDEX_TEMP <= 0 ;
                    DCONV_INDEX <= INDEX_TEMP ; 
                end
            end
            4'b0101,4'b0111:                
            begin
                if(INDEX_TEMP< 95)
                begin
                INDEX_TEMP  <= INDEX_TEMP + 1 ;
                DCONV_INDEX <= INDEX_TEMP ;
                end
                else
                begin
                    INDEX_TEMP <= 0 ;
                    DCONV_INDEX <= INDEX_TEMP ; 
                end
            end
            4'b1001,4'b1011:                
            begin
                if( INDEX_TEMP< 191)
                begin
                    INDEX_TEMP <= INDEX_TEMP + 1 ;
                    DCONV_INDEX <= INDEX_TEMP ;
                end
                else
                begin
                    INDEX_TEMP <= 0 ;
                    DCONV_INDEX <= INDEX_TEMP ; 
                end
            end
            4'b0001,4'b0011:                
            begin
                if(INDEX_TEMP< 287 )
                begin
                    INDEX_TEMP <= INDEX_TEMP + 1 ;
                    DCONV_INDEX <= INDEX_TEMP ;
                end
                else
                begin
                    INDEX_TEMP <= 0 ;
                    DCONV_INDEX <= INDEX_TEMP ; 
                end
            end
               endcase
           end
           else 
               DCONV_INDEX <= 0 ;
   end
end

endmodule