arch/arm/cpu/armv7/start.S
36 .globl _start
37 _start: b reset
136 reset:
137 bl save_boot_params
138 /*
139 * set the cpu to SVC32 mode
140 */
141 mrs r0, cpsr
142 bic r0, r0, #0x1f
143 orr r0, r0, #0xd3
144 msr cpsr,r0
206 call_board_init_f:
207 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
208 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
209 ldr r0,=0x00000000
210 bl board_init_f // ----> 前置初始化 SPL
321 #ifndef CONFIG_SYS_ICACHE_OFF
322 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
323 mcr p15, 0, r0, c7, c10, 4 @ DSB
324 mcr p15, 0, r0, c7, c5, 4 @ ISB
325 #endif
326 ldr r0, _board_init_r_ofs
327 adr r1, _start
328 add lr, r0, r1
329 add lr, lr, r9
330 /* setup parameters for board_init_r */
331 mov r0, r5 /* gd_t */
332 mov r1, r6 /* dest_addr */
333 /* jump to it ... */
334 mov pc, lr
335
336 _board_init_r_ofs:
337 .word board_init_r - _start // 后置初始化， u-boot.img
264 void board_init_f(ulong bootflag)
265 {
// ... ...
281 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
282 if ((*init_fnc_ptr)() != 0) {
283 hang ();
284 }
285 }
// ... ..
235 init_fnc_t *init_sequence[] = {
236 #if defined(CONFIG_ARCH_CPU_INIT)
237 arch_cpu_init, /* basic arch cpu dependent setup */
238 #endif
239 #if defined(CONFIG_BOARD_EARLY_INIT_F)
240 board_early_init_f,
241 #endif
242 timer_init, /* initialize timer */
243 #ifdef CONFIG_FSL_ESDHC
244 get_clocks,
245 #endif
246 env_init, /* initialize environment */
247 init_baudrate, /* initialze baudrate settings */
248 serial_init, /* serial communications setup */
249 console_init_f, /* stage 1 init of console */
250 display_banner, /* say that we are here */
251 #if defined(CONFIG_DISPLAY_CPUINFO)
252 print_cpuinfo, /* display cpu info (and speed) */
253 #endif
254 #if defined(CONFIG_DISPLAY_BOARDINFO)
255 checkboard, /* display board info */
256 #endif
257 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
258 init_func_i2c,
259 #endif
260 dram_init, /* configure available RAM banks */
261 NULL,
262 };
// board/aplex/ecm_5410.c
98 int dram_init(void)
99 {
100 gd->ram_size = PHYS_DRAM_1_SIZE;
101
102 return 0;
103 }
// arch/arm/lib/board.c
443 void board_init_r(gd_t *id, ulong dest_addr)
444 {
// ... ...
464 board_init(); /* Setup chipselects */ // i2c, pinmux gpmc init
// ... ...
523 #if defined(CONFIG_CMD_NAND)
524 puts("NAND : ");
525 nand_init(); /* go init the NAND */
526 #endif
// ... ...
// drivers/mtd/nand/ti81xx_nand.c
864 int board_nand_init(struct nand_chip *nand)
865 {
867 cs = 0;
876 while (cs < GPMC_MAX_CS) {
877 /* Check if NAND type is set */
878 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
879 /* Found it!! */
880 #ifdef NAND_DEBUG
881 printf("Searching for NAND device @ GPMC CS:%1d
", cs);
882 #endif
883 break;
884 }
885 cs++;
886 }
887 if (cs >= GPMC_MAX_CS) {
888 printf("NAND: Unable to find NAND settings in "
889 "GPMC Configuration - quitting
");
890 return -ENODEV;
891 }
892
893 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
894 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
895
896 nand->cmd_ctrl = ti81xx_nand_hwcontrol;
897 nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
898 /* If we are 16 bit dev, our gpmc config tells us that */
899 if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) {
900 nand->options |= NAND_BUSWIDTH_16;
901 }
902
903 nand->chip_delay = 100;
904
905 /* required in case of BCH */
906 elm_init();
907
908 /* BCH info that will be correct for SPL or overridden otherwise. */
909 nand->priv = &bch_priv;
910
911 #ifndef CONFIG_SPL_BUILD
912 /* For undocumented reasons we need to currently keep our environment
913 * in 1-bit ECC so we configure ourself thusly. */
914 nand_curr_device = 0;
915 ti81xx_nand_switch_ecc(NAND_ECC_HW, 0);
916 #else
917 /* The NAND chip present requires that we have written data in with
918 * at least 4-bit ECC so we configure outself for that in SPL.
919 */
920 nand->ecc.mode = NAND_ECC_HW_SYNDROME;
921 nand->ecc.layout = &hw_bch8_nand_oob;
922 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
923 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
924 nand->ecc.steps = CONFIG_SYS_NAND_ECCSTEPS;
925 nand->ecc.total = CONFIG_SYS_NAND_ECCTOTAL;
926 nand->ecc.hwctl = ti81xx_enable_ecc_bch;
927 nand->ecc.correct = ti81xx_correct_data_bch;
928 nand->ecc.calculate = ti81xx_calculate_ecc_bch;
929
930 if (nand->options & NAND_BUSWIDTH_16)
931 nand->read_buf = nand_read_buf16;
932 else
933 nand->read_buf = nand_read_buf;
934 nand->dev_ready = ti81xx_spl_dev_ready;
935
936 ti81xx_hwecc_init_bch(nand, NAND_ECC_READ);
937 #endif
938
939 return 0;
940 }