详细讲解参照从零开始走进FPGA世界，一下是我参照现有20MHz的板子的程序，
/***************************************************
* Module Name : clk_generator
* Engineer : catarget
* Target Device : EP2C8Q208C8
* Tool versions : Quartus II 9.0
* Create Date : 2011-12-3
* Revision : v1.0
* Description :
**************************************************/
/*************************************************
fc = 20MHz 20*10^6
fo = fc*K/(2^32) (0.004657Hz ~ 10MHz)
K = fo*(2^32)/fc
= fo*(2^32)/(20*10^6)
**************************************************/
module clk_generator(
input clk, //20MHz
input rst_n, //RESET
output reg clk_out
);
parameter FREQ_WORD = 32'd214748; //1Hz 214.748,
/*----------------------------------------
32'd214748~1s~1Hz,
32'd21475~10s~0.1Hz,
32'd2147~100s~0.01Hz
32'd214748*N ~ NHz
------------------------------------------*/
//---------------------------------------------------
reg [31:0] max_value;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) max_value <= 1'b0;
else max_value <= max_value + FREQ_WORD;
end
//-------------------------------------------
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) clk_out <= 1'b0;
else begin
if (max_value <= 32'h7FFF_FFFF) clk_out <= 1'b0;
else clk_out <= 1'b1;
end
end
endmodule
通过对FREQ_WORD的修改达到任意分频的目的。