always @(*) begin
case(state)
A: out=0;
if (in)
nest_state=A;
else
next_state=B;
B: out=1;
if(in)
next_state=B;
else
next_state=A;
default:out=0;
endcase
end
always @(posedge clk, posedge areset) begin
if(arset)
state=A;
else
state=next_state;
end
endmodule