AXI : Advanced eXtensible Interface
? 它的地址/控制和数据相位是分离的，支持不对齐的数据传输
? 同时在突发传输中，只需要首地址，同时分离的读写数据通道、并支持显著传输访问和乱序访问
?并更加容易就行时序收敛
? AXI4-Lite, AXI4-Stream
? how seperate channels benifit?
charpter-1 architecture, features
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* separate address/control and data phases
* support for unaligned data transfers using byte strobes
* burst-based transactions with only start address issued
* separate read and write data channels to enable low-cost Direct Memory Access(DMA)
* ability to issue multiple outstanding addresses
* out-of-order transaction completion
* easy addition of register stages to provide timing closure.
--- also some feature for low power, cache support, protection unit support, atomic operation, error support ,u
prefix
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prefix - AW/AR: write write addr/cmd channel(two channels)
prefix - B: write response channel
prefix - R:
prefix - W:
ID transaction
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ordering transaction -
1. 一个master可以同时与不同的的slave操作，这些slave可以有快慢之分。
2. master对同一个复杂的slave操作，传输的速度可以有差别，有些数据是slave内部产生，有些譬如memory从外部获取。
3. 对于有多个master的总线结构，可能master发出的ID是相同的，但是AXI总线可以对master添加prefix，以便么slave可以区分出不同的master
4. ID是spec中规定，具体情况可以变通，如果是简单master，可以对所有的ID置相同的值，如果是简单的slave，可以忽略ID
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awlock,
awchche,
awport,
?为什么write data channel 和write response channel 要区分开来？
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chapter3 - handshake (所有的channel基于 ready-valid)
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1.所有的valid不能依赖于ready信号以防止死锁
2.Two relationships that must be maintained are:
。 read data must always follow the address to which the data relates
。 a write response must always follow the last write transfer in the write transaction to which the write response relates.
chapter4 - address caculate
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AR/AWLEN : 1-16
AR/AWSIZE : 1-16 (1,2,4,…,128 Bytes)
AR/AWBURST : FIXED, INCR, WRAP
wrap boundary: LEN × SIZE (进位无效)
atomic(normal) access/exclusive access/locked access
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indicated by AR/AWLOCK[1:0]
from the perspective of master, if exclusive read at a address, can only followd by exclusive write and return EXOKAY
from the perspective of slave, it must monitor the hardware(for each ID and address)
exclusive access：在一个master读取一个地址的某个数据之后，监视这个地址，如果接下来写这个地址，发现现在的值和刚刚读出来的不一样，那么就 exclusive err
respond signals
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1. for each write burst there only 1 response signal, but for read burst there 1 response signal for each data
2. OKAY, EXOKAY, slave ERR, decode err
★ordering model
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?how to process out-of-order transaction
{AWID, WID, BID} {ARID, RID}
-read and write inter-action
read finished is marked by RLast, write finished is marked by BResp
interconnect usage of
某一次的burst 读/写操作，可以不完全完成，比如burst 7 write，可以先写3个，然后写其他的一笔数据，接下来写另外ID的一笔数据，然后接下来写原来的生下来的4个数据。
data bus
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