在理解ARM的load-store架构时，我在百度上搜索了很长时间，但是始终找不到一篇像样的中文文章。最后，在用谷歌搜索的英文网站上终于找到了一些蛛丝马迹。让我们先看一下一篇英文资料。
Processor design is strongly tied to the instruction set design. There were many diverse computer designs and hence many different instruction set designs in the past. However, as the technology progress, the analysis of the work load, the actual running programs, which affect the instruction set selection, lead to the converge of instruction set. The most common type of instruction set architecture today belong to three classes :
- Load-Store architecture
- Register-Memory architecture
- Register-plus-Memory architecture
Load-Store architecture has 3-address format and mostly 32 bit instruction size. This is the most popular among the current microprocessor design, including : HP PA-RISC, IBM RS/6000, SUN Sparc, MIPS R4000, DEC Alpha etc. All data to/from memory must load/store through a register first. The execution (operation) takes operands from registers and the result stored back to a register. This instruction format simplifies the decoding and implementation.
Register-Memory architecture has 2-address format and has 16/32/64 bit instruction size. An instruction can operate both on registers and with one of the operand in the memory. This is the 'classical' ISA and is used by one of the longest lived ISA of today IBM S/360 and Intel x86 family of processors.
Register-plus-Memory architecture is the most flexible in the use of operands. Operands and be register or memory and has byte-variable instruction size. This flexibility comes with a prize, the complexity in implementation. This type of architecture is typified by VAX family of computer in the era that there was the drive to provide the high level language semantic for the instruction set, so called 'close the gap' between high level language and machine language.
翻译成中文的意思大概是这样的。
Load-Store architecture CPU只允许用load/store指令来与memory(Flash、RAM)交互，而CPU的运算全部都是在寄存器中完成。也就是说，CPU运算的操作数只能全部来自寄存器，而且结构也只能保存在寄存器中。所以，倘若要把RAM两个数据相加，结果还保存到内存中，就需要先将内存中的数据通过load指令将内存数据加载到寄存器中，计算结束后，再将保存结果寄存器的内容通过store指令存储在RAM中。举一个ARM指令的例子如下。
ADD R0,R1,R2Register-Memory architecture CPU的运算操作数可以全部都是寄存器，也允许其中的一个操作数在memory中。所以，CPU可以通过其他指令来与memeory交互，这种架构的指令集相对复杂。举一个X86指令的例子如下。
add mem,reg
Register-plus-Memory architecture CPU的运算操作数可以全部都是寄存器，也可以全部都是memory，还可以两者都有。而且，寄存器、memory的size是可变的，可以是单字节、两个字节、四个字节。所以，CPU和memeory的交互比"Register-Memory architecture"更灵活。这种架构的指令集非常复杂，在译码过程中效率很低。举一个VAX指令的例子如下。
XORL3 (R3)+,(R4)+,(R5)+
附上一个各种ISA(Instruction Set Architecture)的结构图：
参考网站：http://en.wikipedia.org/wiki/Load/store_architecture （Load-Store architecture）
http://en.wikipedia.org/wiki/Register_memory_architecture(Register-Memory architecture )
http://www.cp.eng.chula.ac.th/~piak/teaching/ca/arch-description.htm (Instruction Set Architecture )