module clk_valid_generator
#(parameter N = 16'd2)
(
input clk_in,
input locked,
output reg clk_valid
);
reg [15:0] counter;
always @ (posedge clk_in)
begin
if(locked == 1'b0)
begin
clk_valid <= 1'b0;
counter <= 16'd0;
end
else
begin
if(counter == 16'd0)
clk_valid <= 1'b1;
else
clk_valid <= 1'b0;
if(counter == N - 16'd1)
counter <= 16'd0;
else
counter <= counter + 16'd1;
end
end
endmodule
//顶层例化:
//48MHz分2.4MHz
clk_valid_generator
#(
.N(16'd20)
)
clk_div_20
(
.clk_in(clk_48),
.locked(locked),
.clk_valid(clk_2p4_valid)
);