module myuart_rece( input Gclk, //system clock input rst_n, //glabol reset signal input rx, //serical data in output reg tx, //serical data out output reg DataReady, //a complete byte has been received output reg[7:0] DataReceived, //Bytes received output reg gnd=1'b0 //可以不写 ); /* general sample clock 50MHz分频成3.125MHz*/ reg[7:0] count; reg clk16x; //sample clock always@(posedge Gclk or posedge rst_n) if(rst_n) begin count<=8'd0; clk16x<=1'b0; end else if(count>=8'd125) begin count<=8'd0; clk16x <= ~clk16x; end else count<=count+1'b1; /*how to find the negedge*/ reg trigger_r0; wire neg_tri; always@(posedge clk16x or posedge rst_n) begin if(rst_n) trigger_r0<=1'b0; else trigger_r0<=rx; end assign neg_tri = trigger_r0 & ~rx; /* counter control*/ reg cnt_en; always@(posedge Gclk or posedge rst_n) begin if(rst_n) cnt_en<=1'b0; else if(neg_tri==1'b1) cnt_en<=1'b1; else if(cnt==8'd152) cnt_en<=1'b0; end /* counter module*/ reg[8:0] cnt; always@(posedge clk16x or posedge rst_n) begin if(rst_n) cnt<=8'd0; else if(cnt_en) cnt<=cnt+1'b1; else cnt<=8'd0; end /* receive module*/ reg StopBit_r; always@(posedge clk16x or posedge rst_n) begin if(rst_n) begin DataReceived<=8'b0; tx <= 1'b1; end else if(cnt_en) case(cnt) 9'd24: DataReceived[0] <= rx; 9'd40: DataReceived[1] <= rx; 9'd56: DataReceived[2] <= rx; 9'd72: DataReceived[3] <= rx; 9'd88: DataReceived[4] <= rx; 9'd104: DataReceived[5] <= rx; 9'd120: DataReceived[6] <= rx; 9'd136: DataReceived[7] <= rx; endcase end //判断接受结束 always@(posedge Gclk or posedge rst_n) begin if(rst_n) DataReady<=1'b1; else if(cnt>=8'd152) DataReady<=1'b0; else DataReady<=1'b1; end endmodule
//