每日一摘：串并-并串转换

1、并转串

代码：

module parallel_serial(
clk, rst_n, en, data_i, data_o
    );
input clk, rst_n,en;
input [7:0] data_i;
output  data_o;

reg [7:0]  data_buf;
always @(posedge clk or negedge rst_i) begin
    if (rst_i == 1'b0) begin
        data_o <= 1'b0;
        data_buf <= 8'b0;
    end
    else if (en == 1'b1)
        data_buf <= data_i;
    else
        data_buf <= data_buf <<1;     //将寄存器内的值左移，依次读出
        //data_buf <= {data_buf[6:0],1'b0};
end

assign data_o = data_buf[7];

endmodule

2、串转并

代码：

module serial_parallel(
    input           clk,
    input           rst_n,en,
    input           data_i,   //一位输入
    output   reg [7:0] data_o    //8位并行输出
    );

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        data_o <= 8'b0;
    else if (en == 1'b1)
        data_o <= {data_o[6:0], data_i};    //低位先赋值
    else
        data_o <= data_o;
end

endmodule