Chapter 9 Exceptions and Interrupts
第9章 异常和中断
Interrupts and exceptions are special kinds of control transfer; they work somewhat like unprogrammed CALLs. They alter the normal program flow to handle external events or to report errors or exceptional conditions. The difference between interrupts and exceptions is that interrupts are used to handle asynchronous events external to the processor, but exceptions handle conditions detected by the processor itself in the course of executing instructions.
中断和异常是特殊的控制转移；他们的工作方式有点象不是预先编程好的CALL调用。他们改变程序流程来处理外部事件或来报告错误和异常的环境。中断和异常的不同之处在于中断被用来处理处理器外部的异步事件，而异常处理的是处理器自身在执行指令期间侦测到的状况。
There are two sources for external interrupts and two sources for exceptions:
外部中断和异常的两个来源：
- Interrupts 中断
- Maskable interrupts, which are signalled via the INTR pin.
可屏蔽的中断，通过INTR引脚来发送信号。
- Nonmaskable interrupts, which are signalled via the NMI (Non-Maskable Interrupt) pin.
不可屏蔽中断，通过NMI引脚来发送信号。
- Exceptions 异常
- Processor detected. These are further classified as faults, traps, and aborts.
处理器侦测到的。进一步分类为错误、陷阱和忽略。
- Programmed. The instructions INTO, INT 3, INT n, and BOUND can trigger exceptions. These instructions are often called "software interrupts", but the processor handles them as exceptions.
程序化的。指令INT0、INT3、INTn以及BOUND，可以触发异常。这些指令经常被叫做“软件中断”，但处理器把它们做为异常处理。
This chapter explains the features that the 80386 offers for controlling and responding to interrupts when it is executing in protected mode.
本章解释当在保护模式下运行时，80386提供的用来控制和回应中断的特性。
9.1 Identifying Interrupts 标识中断
The processor associates an identifying number with each different type of interrupt or exception.
处理器将每个不同类型的中断或异常和标识数值联系起来。
The NMI and the exceptions recognized by the processor are assigned predetermined identifiers in the range 0 through 31. Not all of these numbers are currently used by the 80386; unassigned identifiers in this range are reserved by Intel for possible future expansion.
处理器识别的NMI和异常被用预先定义的0到31个数值来标识。当前80386没有使用所有的这些数值；在这个范围中未分配的标识被保留给将来使用。
The identifiers of the maskable interrupts are determined by external interrupt controllers (such as Intel's 8259A Programmable Interrupt Controller) and communicated to the processor during the processor's interrupt-acknowledge sequence. The numbers assigned by an 8259A PIC can be specified by software. Any numbers in the range 32 through 255 can be used. Table 9-1 shows the assignment of interrupt and exception identifiers.
外部中断控制器（例如英特8259A可编程中断控制器）决定可屏蔽中断的标识，并在处理器的中断确认周期中与处理器通信。8259A PIC分配的数值可以被软件指定。任何32与255之间的数值都可以使用。表9-1展示了中断与异常标识的分配。
Table 9-1. Interrupt and Exception ID Assignments
Identifier Description
0 Divide error 除法错误
1 Debug exceptions 调试异常
2 Nonmaskable interrupt 不可屏蔽中断
3 Breakpoint (one-byte INT 3 instruction) 断点（一个字节的INT3指令）
4 Overflow (INTO instruction) 溢出（INTO指令）
5 Bounds check (BOUND instruction)边界检验（BOUND指令）
6 Invalid opcode 非法操作符
7 Coprocessor not available 协处理器不可用
8 Double fault 双重错误
9 (reserved) （保留）
10 Invalid TSS 无效的TSS
11 Segment not present 段不存在
12 Stack exception 栈异常
13 General protection 一般性保护
14 Page fault 页错误
15 (reserved) （保留）
16 Coprecessor error 协处理器错误
17-31 (reserved) （保留）
32-255 Available for external interrupts via INTR pin 对通过INTR引脚触发的外部中断有效
Exceptions are classified as faults, traps, or aborts depending on the way they are reported and whether restart of the instruction that caused the exception is supported.
按照被报告方式和是否支持重新运行引起异常的指令，异常被分为错误、陷阱或忽略。
Faults 错误
Faults are exceptions that are reported "before" the instruction causing the exception. Faults are either detected before the instruction begins to execute, or during execution of the instruction. If detected during the instruction, the fault is reported with the machine restored to a state that permits the instruction to be restarted.
错误是指令引发异常之前就被报告的异常。错误即可以在指令执行前被侦测，也可以在执行执行期间被侦测。如果在执行期间侦测到，错误被报告时，机器保存状态以允许指令被重新执行。
Traps 陷阱
A trap is an exception that is reported at the instruction boundary immediately after the instruction in which the exception was detected.
（真不会翻译了。）
Aborts 忽略
An abort is an exception that permits neither precise location of the instruction causing the exception nor restart of the program that caused the exception. Aborts are used to report severe errors, such as hardware errors and inconsistent or illegal values in system tables.
忽略异常即不精确定位指点发异常的指令，也不重新运行引发异常的程序。忽略用来报告严重错误，如硬件错误和系统表中不一致或非法的值。
9.2 Enabling and Disabling Interrupts
The processor services interrupts and exceptions only between the end of one instruction and the beginning of the next. When the repeat prefix is used to repeat a string instruction, interrupts and exceptions may occur between repetitions. Thus, operations on long strings do not delay interrupt response.
处理器仅在一条指令结束与下一条指令开始前才响应中断和异常。（换言之，处理器仅在两条指令之间才响应中断和异常。）当使用重复前缀来重复一个字符串指令时，中断和异常可以发生在两个重复之间。这样，长的字符串操作不会延迟中断响应。
Certain conditions and flag settings cause the processor to inhibit certain interrupts and exceptions at instruction boundaries.
某此条件和标志的设定会导致处理器禁止某些特定中断和异常在指令边界发生。
9.2.1 NMI Masks Further NMIs
NMI屏蔽进一步的NMI信号
While an NMI handler is executing, the processor ignores further interrupt signals at the NMI pin until the next IRET instruction is executed.
当NMI处理器运行时，处理器忽略NMI引脚上进一步的中断信号，直到下一个IRET指令被执行。（换言之，NMI不能嵌套处理。）
9.2.2 IF Masks INTR
IF位屏蔽INTR
The IF (interrupt-enable flag) controls the acceptance of external interrupts signalled via the INTR pin. When IF=0, INTR interrupts are inhibited; when IF=1, INTR interrupts are enabled. As with the other flag bits, the processor clears IF in response to a RESET signal. The instructions CLI and STI alter the setting of IF.
IF（中断使能标志）控制着是否接受外部中断通过INTR引脚发送的信号。当IF为0时，INTR中断被禁止；当IF等于1时，INTR中断被激活。和其他标志位一起，处理器在响应REST信号时清除IF标志。指令CLI和STI变更IF的设置。
CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag) explicitly alter IF (bit 9 in the flag register). These instructions may be executed only if CPL <= IOPL. A protection exception occurs if they are executed when CPL > IOPL.
CLI（清除中断使能标志）和STI（设置中断使能标志）仅更改IF（标志寄存器的第9位）。这些指令只能在CPL小于或等于IOPL时被执行。当CPL大于IOPL时这些指令的执行会引发保护异常。
The IF is also affected implicitly by the following operations:
IF也会隐式地受以下操作影响：
- The instruction PUSHF stores all flags, including IF, in the stack where they can be examined.
指令PUSHF将所有标志（包括IF）保存在栈内（在那里他们可以被检查）。
- Task switches and the instructions POPF and IRET load the flags register; therefore, they can be used to modify IF.
任务切换和指令POPF及IRET装入标志寄存器；因此，他们也用来修改IF。
- Interrupts through interrupt gates automatically reset IF, disabling interrupts. (Interrupt gates are explained later in this chapter.)
通过中断门的中断自动重置IF位，关闭中断。（中断门在本章后面会解释。）
9.2.3 RF Masks Debug Faults RF屏蔽调试错误
The RF bit in EFLAGS controls the recognition of debug faults. This permits debug faults to be raised for a given instruction at most once, no matter how many times the instruction is restarted . (Refer to Chapter 12 for more information on debugging.)
EFLAGS中的RF位控制是否识别调试错误。这允许给定的指令最多引发一次调试错误，不管指令重复执行多少次。（参见第12章调试的更多信息）
9.2.4 MOV or POP to SS Masks Some Interrupts and Exceptions
对SS的MOV或POP屏蔽某此中断和异常
Software that needs to change stack segments often uses a pair of instructions; for example:
软件需要使用一对指令来修改栈段；例如：
MOV SS, AX 将AX的内容移给SS寄存器（修改栈段，指向一个新段）
MOV ESP, StackTop 将栈顶数据弹出给ESP（修改栈指针，以指向一个新段的栈顶）
If an interrupt or exception is processed after SS has been changed but before ESP has received the corresponding change, the two parts of the stack pointer SS:ESP are inconsistent for the duration of the interrupt handler or exception handler.
如果在SS被修改之后，ESP接收到一个相应的修改之前，中断或异常被处理，中断或异常处理期间，栈的SS：ESP这对指针将不再一致。
To prevent this situation, the 80386, after both a MOV to SS and a POP to SS instruction, inhibits NMI, INTR, debug exceptions, and single-step traps at the instruction boundary following the instruction that changes SS. Some exceptions may still occur; namely, page fault and general protection fault. Always use the 80386LSS instruction, and the problem will not occur.
为避免这种情况发生，在将栈段移入SS（使用MOV指令）和弹出栈数据到SS（使用POP指令）这两个指令之后，80386在下面修改SS的指令边界上，禁止NMI、INTR、调试异常和单步陷阱。一些异常依旧会发生；一般来说，页错误和一般保护性错误可以发生。80386总是使用LSS指令，这样这些问题不会发生。
9.3 Priority Among Simultaneous Interrupts and Exceptions
同时发生中断和异常时的优先级
If more than one interrupt or exception is pending at an instruction boundary, the processor services one of them at a time. The priority among classes of interrupt and exception sources is shown in Table 9-2. The processor first services a pending interrupt or exception from the class that has the highest priority, transferring control to the first instruction of the interrupt handler. Lower priority exceptions are discarded; lower priority interrupts are held pending. Discarded exceptions will be rediscovered when the interrupt handler returns control to the point of interruption.
如果在一个指令边界有多个中断或异常被挂起，处理器在一个时间里只能处理它们中的一个。表9-2展示了按来源分类的中断和异常的优先级。
Table 9-2. Priority Among Simultaneous Interrupts and Exceptions
Priority Class of Interrupt or Exception
优先级中断或异常的分类
HIGHEST Faults except debug faults
最高级 错误异常 调试错误
Trap instructions INTO, INT n, INT 3
陷阱指令 INTO、INTn、INT3
Debug traps for this instruction
对指令使用的调试陷阱
Debug faults for next instruction
对下一条指令的调试错误
NMI interrupt
NMI中断
LOWEST INTR interrupt
最低 INTR中断